公开(公告)号：US09170496B2

公开(公告)日：2015-10-27

申请号：US13365660

申请日：2012-02-03

Applicant: Chi-Hua Fu ,  Chung-Cheng Wang

Inventor： Chi-Hua Fu ,  Chung-Cheng Wang

IPC: B08B3/02 ,  B08B3/00 ,  B08B7/00 ,  B08B7/04 ,  G03F7/16 ,  G03F7/09 ,  G03F7/095

CPC classification number: G03F7/16 ,  B08B3/00 ,  B08B3/02 ,  B08B7/00 ,  B08B7/04 ,  G03F7/091 ,  G03F7/094 ,  G03F7/095

Abstract: A method for pre-treating a wafer surface before applying a material thereon. The method includes positioning the wafer on a rotating apparatus. The wafer is rotated at a first rotational speed between about 50 revolutions per minute (rpm) and about 300 rpm and for a period of about 1 second to about 10 seconds while dispensing a cleaning solvent on the wafer surface. The wafer is rotated at a second rotational speed between about 500 rpm and about 1,500 rpm for a period of about 1 second to about 10 seconds. The wafer is then rotated at a third rotational speed between about 50 rpm and about 300 rpm for a period of about 1 second to about 5 seconds. With the wafer rotating at the third rotational speed, a solvent-containing material is thereafter deposited on the surface of the wafer.

Abstract translation: 一种在施加材料之前预处理晶片表面的方法。 该方法包括将晶片定位在旋转装置上。 以约50转/分钟（rpm）和约300rpm之间的第一旋转速度旋转晶片，并且在晶片表面上分配清洁溶剂约1秒至约10秒的时间。 晶片以约500rpm至约1500rpm之间的第二转速旋转约1秒至约10秒的时间。 然后将晶片以约50rpm至约300rpm之间的第三转速旋转约1秒至约5秒的时间。 随着晶片以第三转速旋转，此后在晶片的表面上沉积含溶剂的材料。

公开(公告)号：US20220387756A1

公开(公告)日：2022-12-08

申请号：US17830845

申请日：2022-06-02

Applicant: Chung-Cheng Wang ,  Yung-Ping Wang ,  Yi-Yuan Chen ,  Chia-Ming Hsu ,  Ming-Chien Chiu ,  Chia-Ch Lin

Inventor： Chung-Cheng Wang ,  Yung-Ping Wang ,  Yi-Yuan Chen ,  Chia-Ming Hsu

IPC: A61M25/01

Abstract: A urinary catheter conveying device includes a sleeve member, a conveying assembly and a controller. The sleeve member is for sleeving onto a glans of a penis and has a guiding hole to be registered with an external urethral orifice of the glans. The conveying assembly includes a casing removably mounted to the sleeve member, and a conveying mechanism for advancing the urinary catheter to the guiding hole such that the urinary catheter is inserted into the external urethral orifice. The controller controls the conveying mechanism to advance the urinary catheter to the guiding hole. A urinary catheterization system and a method of using the urinary catheterization system are also disclosed.

公开(公告)号：US07301415B2

公开(公告)日：2007-11-27

申请号：US11164924

申请日：2005-12-12

Applicant: Chung-Cheng Wang ,  Chao-Shi Chuang ,  Wen-Shih Lu ,  Yu-Chang Chen

Inventor： Chung-Cheng Wang ,  Chao-Shi Chuang ,  Wen-Shih Lu ,  Yu-Chang Chen

IPC: H03B1/00

CPC classification number: H03L7/10

Abstract: A method for automatic frequency tuning in a phase lock loop suitable for use in multi-band VCO wireless systems having very limited initial frequency lock times is disclosed. A predetermined subset of VCOs out of a larger bank of VCOs is selected to serve as interpolation points. The interpolation point VCOs are pre-calibrated with a predetermined voltage and the resultingly generated frequency for each of the interpolation point VCOs is stored into memory as a (frequency, VCO) pair, one pair for each interpolation point VCO. When a desired frequency then is given to the system, an appropriate VCO is selected by interpolation using the (frequency, VCO) pairs of the two most adjacent interpolation points for tracking and locking.

Abstract translation: 公开了一种适用于具有非常有限的初始频率锁定时间的多频带VCO无线系统的锁相环中的自动频率调谐方法。 选择较大的VCO组中的VCO的预定子集用作内插点。 内插点VCO以预定电压进行预校准，并且每个内插点VCO的最终产生的频率作为（频率，VCO）对存储到存储器中，对于每个内插点VCO为一对。 当给系统给出期望的频率时，通过使用用于跟踪和锁定的两个最相邻插值点的（频率，VCO）对进行插值来选择适当的VCO。

公开(公告)号：US07047146B2

公开(公告)日：2006-05-16

申请号：US10707519

申请日：2003-12-19

Applicant: Chao-Shi Chuang ,  Chung-Cheng Wang ,  Wen-Shih Lu

Inventor： Chao-Shi Chuang ,  Chung-Cheng Wang ,  Wen-Shih Lu

IPC: G01R35/00 ,  G06F19/00

CPC classification number: H03L7/113 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/199

Abstract: A PLL includes a loop filter for accumulating charge to generate a loop-filter voltage and a VCO having a plurality of frequency ranges. The VCO receives the loop-filter voltage and generates an output signal having a frequency according to the loop-filter voltage and a currently selected VCO frequency range. During PLL calibration, the loop-filter is connected to a constant voltage source; the PLL feedback signal is synchronized with the reference signal; a linear search, a binary search, or a memory lookup is used to find a first and a second VCO frequency range; first and second time durations are measured for the time durations between the second rising edges of the reference signal and the PLL feedback signal for the two VCO frequency ranges, and the optimal VCO frequency range is determined by setting the VCO frequency range to be the VCO frequency range having the shortest measured time duration.

Abstract translation: PLL包括用于累积电荷以产生环路滤波器电压的环路滤波器和具有多个频率范围的VCO。 VCO接收环路滤波器电压，并产生具有根据环路滤波器电压和当前选择的VCO频率范围的频率的输出信号。 在PLL校准期间，环路滤波器连接到恒定电压源; PLL反馈信号与参考信号同步; 使用线性搜索，二进制搜索或存储器查找来找到第一和第二VCO频率范围; 对于参考信号的第二上升沿和两个VCO频率范围的PLL反馈信号之间的持续时间测量第一和第二持续时间，并且通过将VCO频率范围设置为VCO来确定最佳VCO频率范围 频率范围具有最短的测量持续时间。

公开(公告)号：US5821725A

公开(公告)日：1998-10-13

申请号：US731461

申请日：1996-10-16

Applicant: Chung-Cheng Wang ,  Jin-Chern Chiou ,  Shih-Tung Cheng

Inventor： Chung-Cheng Wang ,  Jin-Chern Chiou ,  Shih-Tung Cheng

IPC: H02P6/10 ,  H02P5/28

CPC classification number: H02P6/10

Abstract: An electric current compensation circuit for use with a multiple-phase burshless motor to reduce ripples in the output torque is disclosed. It contains a plurality of electric current compensation loops each for a respective phase winding and each of the electric compensation loops contains: (a) a first input for receiving a line current from the driver; (b) a second input for receiving the compensation current from the motor sensor; (c) a forward rectifying circuit for forwardly rectifying the line current and the compensation current; (d) a reverse rectifying circuit for reversely rectifying the line current and the compensation current; and (e) a summation circuit for summing the forwardly rectified compensation current and the reversely rectified compensation current and outputting a synthetic current to a phase winding of the motor. Each time the phase is changed, the electric current compensation circuit is triggered causing the synthetic current to be sent to the motor to allow the motor to generate an output torque with reduced ripple.

Abstract translation: 公开了一种与多相无刷电机一起使用以减少输出转矩波纹的电流补偿电路。 它包含多个电流补偿回路，每个电流补偿回路各自用于各自的相绕组，并且每个电补偿回路包含：（a）用于接收来自驾驶员的线电流的第一输入; （b）用于从电动机传感器接收补偿电流的第二输入; （c）正向整流线路电流和补偿电流的正向整流电路; （d）用于反向整流线路电流和补偿电流的反向整流电路; 和（e）用于将前向整流补偿电流和逆整流补偿电流相加的求和电路，并将合成电流输出到电动机的相绕组。 每次相位改变时，触发电流补偿电路，使得合成电流被发送到电动机，以允许电动机产生具有减小的纹波的输出转矩。

公开(公告)号：US12017015B2

公开(公告)日：2024-06-25

申请号：US17830845

申请日：2022-06-02

Applicant: Chung-Cheng Wang ,  Ming-Chien Chiu

Inventor： Chung-Cheng Wang ,  Yung-Ping Wang ,  Yi-Yuan Chen ,  Chia-Ming Hsu

IPC: A61M25/00 ,  A61M25/01 ,  A61M25/02

CPC classification number: A61M25/0113 ,  A61M2025/0001 ,  A61M25/0105 ,  A61M2025/026 ,  A61M2205/3327 ,  A61M2205/583 ,  A61M2205/587 ,  A61M2205/8206 ,  A61M2210/1096 ,  A61M2210/167

Abstract: A urinary catheter conveying device includes a sleeve member, a conveying assembly and a controller. The sleeve member is for sleeving onto a glans of a penis and has a guiding hole to be registered with an external urethral orifice of the glans. The conveying assembly includes a casing removably mounted to the sleeve member, and a conveying mechanism for advancing the urinary catheter to the guiding hole such that the urinary catheter is inserted into the external urethral orifice. The controller controls the conveying mechanism to advance the urinary catheter to the guiding hole. A urinary catheterization system and a method of using the urinary catheterization system are also disclosed.

公开(公告)号：US07180376B2

公开(公告)日：2007-02-20

申请号：US11034484

申请日：2005-01-13

Applicant: Chong-Ren Wang ,  Chao-Shi Chuang ,  Chung-Cheng Wang

Inventor： Chong-Ren Wang ,  Chao-Shi Chuang ,  Chung-Cheng Wang

IPC: H03L7/00

CPC classification number: H03L7/1976 ,  H03L7/0898

Abstract: Synthesizer and calibrating method utilizing same. The frequency synthesizer modulates input signals comprising a phase locked loop circuit. The phase locked loop circuit comprises a phase frequency detector for generating a first signal, a low pass filter for outputting a filtered control signal derived from the received first signal, a voltage control oscillator for generating an output signal with a first frequency based on the control signal, a frequency divider dividing the first frequency for output to the input terminal of the phase frequency detector, a modulator coupled to the frequency divider, a pre-emphasis filter receiving and filtering the input signal for output to the modulator, and an auto loop gain calibration circuit, receiving the control signal, and calculating a current gain of the control signal in accordance with the voltage of the control signal to compensate for the frequency response mismatch between the pre-emphasis filter and the frequency synthesizer.

Abstract translation: 合成器和校准方法利用它。 频率合成器调制包括锁相环电路的输入信号。 锁相环电路包括用于产生第一信号的相位频率检测器，用于输出从接收到的第一信号导出的经滤波的控制信号的低通滤波器，用于基于控制产生具有第一频率的输出信号的电压控制振荡器 信号，将第一频率分频输出到相位频率检测器的输入端的分频器，耦合到分频器的调制器，预加重滤波器接收和滤波输入信号以输出到调制器，以及自动回路 增益校准电路，接收控制信号，以及根据控制信号的电压计算控制信号的当前增益，以补偿预加重滤波器和频率合成器之间的频率响应失配。

公开(公告)号：US20060279446A1

公开(公告)日：2006-12-14

申请号：US11451362

申请日：2006-06-13

Applicant: Chung-Cheng Wang ,  John-San Yang

Inventor： Chung-Cheng Wang ,  John-San Yang

IPC: H03M1/12

CPC classification number: H04B1/28 ,  H04B1/0028 ,  H04B1/0032

Abstract: A radio frequency (RF) receiver is provided, comprising an antenna, a low noise amplifier, a down converter, a first analog to digital converter (ADC), a second ADC, a digital up converter. The antenna receives an RF signal, and the LNA coupled to the antenna amplifies the RF signal. The down converter, coupled to the LNA, down converts the RF signal to generate an in-phase baseband signal and a quadrature baseband signal. The first ADC, coupled to the down converter, digitizes the in-phase baseband signal to an in-phase digital signal. The second ADC, coupled to the down converter, digitizes the quadrature baseband signal to a quadrature digital signal. The digital up converter, coupled to the first and second ADCs, up converts the in-phase digital signal and quadrature digital signal to generate an intermediate frequency (IF) signal.

Abstract translation: 提供了一种射频（RF）接收机，包括天线，低噪声放大器，下变频器，第一模数转换器（ADC），第二ADC，数字上变频器。 天线接收RF信号，耦合到天线的LNA放大RF信号。 耦合到LNA的下变频器将RF信号下变频以产生同相基带信号和正交基带信号。 耦合到下变频器的第一个ADC将同相基带信号数字化为同相数字信号。 耦合到下变频器的第二个ADC将正交基带信号数字化为正交数字信号。 耦合到第一和第二ADC的数字上变频器向上转换同相数字信号和正交数字信号以产生中频（IF）信号。

公开(公告)号：US20050156676A1

公开(公告)日：2005-07-21

申请号：US11034484

申请日：2005-01-13

Applicant: Chong-Ren Wang ,  Chao-Shi Chuang ,  Chung-Cheng Wang

Inventor： Chong-Ren Wang ,  Chao-Shi Chuang ,  Chung-Cheng Wang

IPC: H03L7/00 ,  H03L7/089 ,  H03L7/16 ,  H03L7/197

CPC classification number: H03L7/1976 ,  H03L7/0898

Abstract: Synthesizer and calibrating method utilizing same. The frequency synthesizer modulates input signals comprising a phase locked loop circuit. The phase locked loop circuit comprises a phase frequency detector for generating a first signal, a low pass filter for outputting a filtered control signal derived from the received first signal, a voltage control oscillator for generating an output signal with a first frequency based on the control signal, a frequency divider dividing the first frequency for output to the input terminal of the phase frequency detector, a modulator coupled to the frequency divider, a pre-emphasis filter receiving and filtering the input signal for output to the modulator, and an auto loop gain calibration circuit, receiving the control signal, and calculating a current gain of the control signal in accordance with the voltage of the control signal to compensate for the frequency response mismatch between the pre-emphasis filter and the frequency synthesizer.

Abstract translation: 合成器和校准方法利用它。 频率合成器调制包括锁相环电路的输入信号。 锁相环电路包括用于产生第一信号的相位频率检测器，用于输出从接收到的第一信号导出的经滤波的控制信号的低通滤波器，用于基于控制产生具有第一频率的输出信号的电压控制振荡器 信号，将第一频率分频输出到相位频率检测器的输入端的分频器，耦合到分频器的调制器，预加重滤波器接收和滤波输入信号以输出到调制器，以及自动回路 增益校准电路，接收控制信号，以及根据控制信号的电压计算控制信号的当前增益，以补偿预加重滤波器和频率合成器之间的频率响应失配。

公开(公告)号：US07511579B2

公开(公告)日：2009-03-31

申请号：US11455730

申请日：2006-06-20

Applicant: Chung-Cheng Wang ,  Chao-Shi Chuang ,  Yi-Chuan Liu

Inventor： Chung-Cheng Wang ,  Chao-Shi Chuang ,  Yi-Chuan Liu

IPC: H03L7/08

CPC classification number: H03L7/113 ,  H03L7/1972

Abstract: A PLL is provided, comprising a first divider, a PFD, a loop filter, a VCO, a second divider and a controller. The first divider receives a reference signal and divides the reference signal by R to obtain a divided signal. The PFD compares the divided signal and a feedback signal to generate a compared The VCO selects one of a plurality of operating curves for oscillation based on a selection signal, and generates an oscillation signal based on an operating voltage generated by signal the loop filter. The second divider divides the oscillation signal by N to obtain the feedback signal. The controller operates in an initial mode to recursively determine the selection signal by calculating differences of the feedback signal and the divided signal. When the selection signal converges to stable, the PLL switches to a normal mode to operate on the corresponding operating curve.

Abstract translation: 提供PLL，包括第一分频器，PFD，环路滤波器，VCO，第二分频器和控制器。 第一分频器接收参考信号并将参考信号除以R以获得分频信号。 PFD比较分频信号和反馈信号以产生比较VCO基于选择信号选择多个用于振荡的操作曲线中的一个，并且基于由环路滤波器的信号产生的工作电压产生振荡信号。 第二分频器将振荡信号除以N以获得反馈信号。 控制器以初始模式工作，通过计算反馈信号和分频信号的差异递归地确定选择信号。 当选择信号收敛到稳定时，PLL切换到正常模式，以对相应的工作曲线进行操作。