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    EMBEDDED TURBINE GENERATOR SET
    1.
    发明申请
    EMBEDDED TURBINE GENERATOR SET 审中-公开
    嵌入式涡轮发电机组

    公开(公告)号：US20110042953A1

    公开(公告)日：2011-02-24

    申请号：US12790916

    申请日：2010-05-31

    申请人： Chi-Rong Kuo ,  Chih-Wei Yen ,  Ta-Wei Wang ,  Yuh-Ren Lee ,  Buo-Hua Hsu

    发明人： Chi-Rong Kuo ,  Chih-Wei Yen ,  Ta-Wei Wang ,  Yuh-Ren Lee ,  Buo-Hua Hsu

    IPC分类号： F01D15/10 ,  H02K7/18

    CPC分类号： H02K7/1823 ,  F01D15/10 ,  F03B13/00 ,  F05B2220/20 ,  F05B2220/602 ,  F05D2220/20 ,  F05D2220/62 ,  H02K5/22 ,  Y02B10/50

    摘要： This disclosure relates to a turbine generator set, in which an axial-flow turbine and a generator are embedded inside a flow channel. In an exemplary embodiment of the disclosure, the turbine generator set comprises: a flow channel being provided with a front end as an inlet duct and a back end as an outlet duct; an axial-flow turbine, being single-stage or multi-stage, capable of transforming thermal and pressure energies of a working fluid inside the flow channel into rotational energy; and a generator, comprising a rotor and a stator, being capable of transforming the rotational energy into electricity. A shaft of the turbine and a shaft of the generator can be coupled directly or by way of a gear set. Electricity is transmitted from the flow channel by way of a bunch of cables passing through the flow channel.

    摘要翻译： 本公开涉及一种涡轮发电机组，其中轴流涡轮机和发电机被嵌入在流动通道内。 在本公开的示例性实施例中，涡轮发电机组包括：流动通道，其设置有作为入口管道的前端和作为出口管道的后端; 单级或多级的轴流涡轮机，其能够将流动通道内的工作流体的热能和压力能量转换成旋转能量; 以及包括转子和定子的发电机，其能够将旋转能量转换成电。 涡轮机的轴和发电机的轴可以直接或通过齿轮组联接。 电流通过一束通过流路的电缆从流路传输。

    High Performance CMOS Device Design
    4.
    发明申请
    High Performance CMOS Device Design 有权
    高性能CMOS器件设计

    公开(公告)号：US20090090935A1

    公开(公告)日：2009-04-09

    申请号：US12330961

    申请日：2008-12-09

    申请人： Chih-Hao Wang ,  Shang-Chih Chen ,  Ching-Wei Tsai ,  Ta-Wei Wang ,  Pang-Yen Tsai

    发明人： Chih-Hao Wang ,  Shang-Chih Chen ,  Ching-Wei Tsai ,  Ta-Wei Wang ,  Pang-Yen Tsai

    IPC分类号： H01L29/78

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/66553 ,  H01L29/66636

    摘要： A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer.

    摘要翻译： 半导体器件包括栅极，栅极包括位于栅极电极下方的栅极电极和栅极电介质，形成在栅极电极和栅极电介质的侧壁上的间隔物，缓冲层，其具有位于栅极电介质下方的第一部分和间隔物 以及与间隔物相邻的第二部分，其中缓冲层的第二部分的顶表面在缓冲层的第一部分的顶表面下方凹陷，并且基本上与间隔物对准的源极/漏极区域。 缓冲层优选具有比下面的半导体衬底更大的晶格常数。 半导体器件还可以包括在缓冲层和栅极电介质之间的半导体覆盖层，其中半导体覆盖层具有比缓冲层更小的晶格常数。

    High performance transistors with SiGe strain
    5.
    发明申请
    High performance transistors with SiGe strain 有权
    具有SiGe应变的高性能晶体管

    公开(公告)号：US20060194387A1

    公开(公告)日：2006-08-31

    申请号：US11066062

    申请日：2005-02-25

    申请人： Chih-Hao Wang ,  Ta-Wei Wang

    发明人： Chih-Hao Wang ,  Ta-Wei Wang

    IPC分类号： H01L21/336 ,  H01L29/76

    CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843

    摘要： A preferred embodiment of the invention comprises a semiconductor device having stress in the source/drain channel. The device comprises a substrate having a lattice constant greater than or equal to silicon and a first layer on the substrate, wherein the first layer has a lattice constant greater than the substrate. Alternative embodiments include a second layer formed on the first layer. The second layer has a lattice constant less than the first layer. Preferably, the second layer underlies a gate electrode and at least a portion of a sidewall spacer. Still other embodiments include a recess for inducing stress in the source/drain channel.

    摘要翻译： 本发明的优选实施例包括在源/漏通道中具有应力的半导体器件。 该器件包括具有大于或等于硅的晶格常数的衬底和衬底上的第一层，其中第一层具有大于衬底的晶格常数。 替代实施例包括形成在第一层上的第二层。 第二层具有小于第一层的晶格常数。 优选地，第二层位于栅电极和侧壁间隔物的至少一部分之下。 其他实施例包括用于在源/漏通道中引发应力的凹部。

    Defect-free SiGe source/drain formation by epitaxy-free process
    6.
    发明授权
    Defect-free SiGe source/drain formation by epitaxy-free process 有权
    无缺陷的SiGe源/漏通过无外延生长过程形成

    公开(公告)号：US08900980B2

    公开(公告)日：2014-12-02

    申请号：US11361249

    申请日：2006-02-24

    申请人： Chih-Hao Wang ,  Shih-Hsieng Huang ,  Ta-Wei Wang

    发明人： Chih-Hao Wang ,  Shih-Hsieng Huang ,  Ta-Wei Wang

    IPC分类号： H01L21/00 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66

    CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： MOSFET transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice constant different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe. Implanting a portion of the source/drain regions with Ge forms the embedded stressor. Implanting carbon into the source/drain regions and annealing the substrate after implanting the carbon suppresses dislocation formation, thereby improving device performance.

    摘要翻译： 提供了具有用于改善载流子迁移率的局部应力源的MOSFET晶体管。 本发明的实施例包括形成在衬底上的栅极电极，栅电极下的衬底中的载流子通道区域和载流子通道区域两侧的源极/漏极区域。 源极/漏极区域包括具有不同于衬底的晶格常数的嵌入应力源。 在优选实施例中，衬底是硅，并且嵌入的应力器是SiGe。 用Ge埋设一部分源极/漏极区域形成嵌入的应力源。 在植入碳后将碳植入源极/漏极区域并退火衬底抑制位错形成，从而提高器件性能。

    High performance transistor with a highly stressed channel
    7.
    发明授权
    High performance transistor with a highly stressed channel 有权
    具有高应力通道的高性能晶体管

    公开(公告)号：US07649233B2

    公开(公告)日：2010-01-19

    申请号：US11950467

    申请日：2007-12-05

    申请人： Chih-Hao Wang ,  Ching-Wei Tsai ,  Ta-Wei Wang

    发明人： Chih-Hao Wang ,  Ching-Wei Tsai ,  Ta-Wei Wang

    IPC分类号： H01L27/088

    CPC分类号： H01L29/1054 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843

    摘要： A MOS transistor having a highly stressed channel region and a method for forming the same are provided. The method includes forming a first semiconductor plate over a semiconductor substrate, forming a second semiconductor plate on the first semiconductor plate wherein the first semiconductor plate has a substantially greater lattice constant than the second semiconductor plate, and forming a gate stack over the first and the second semiconductor plates. The first and the second semiconductor plates include extensions extending substantially beyond side edges of the gate stack. The method further includes forming a silicon-containing layer on the semiconductor substrate, preferably spaced apart from the first and the second semiconductor plates, forming a spacer, a LDD region and a source/drain region, and forming a silicide region and a contact etch stop layer. A high stress is developed in the channel region. Current crowding effects are reduced due to the raised silicide region.

    摘要翻译： 提供具有高应力沟道区的MOS晶体管及其形成方法。 该方法包括在半导体衬底上形成第一半导体板，在第一半导体板上形成第二半导体板，其中第一半导体板具有比第二半导体板大得多的晶格常数，以及在第一半导体板上形成栅叠层 第二半导体板。 第一和第二半导体板包括基本上超过栅极堆叠的侧边缘延伸的延伸部。 该方法还包括在半导体衬底上形成优选与第一和第二半导体板隔开的含硅层，形成间隔物，LDD区和源极/漏极区，以及形成硅化物区和接触蚀刻 停止层。 在通道区域产生高应力。 由于硅化物区域的增加，电流拥挤效应降低。

    Smart grading implant with diffusion retarding implant for making integrated circuit chips
    8.
    发明授权
    Smart grading implant with diffusion retarding implant for making integrated circuit chips 有权
    使用扩散阻滞植入物制造集成电路芯片的智能分级植入物

    公开(公告)号：US07320921B2

    公开(公告)日：2008-01-22

    申请号：US11086498

    申请日：2005-03-22

    申请人： Chih-Hao Wang ,  Ta-Wei Wang

    发明人： Chih-Hao Wang ,  Ta-Wei Wang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7833 ,  H01L29/1083 ,  H01L29/6659

    摘要： A method of making an integrated circuit chip is provided, which combines a smart grading implant with a diffusion retarding implant, e.g., to improve short channel effect controllability and improve dopant grading in the source/drain regions. Using a smart grading implant, a relatively low-energy high-dose implant is performed before a relatively low-energy high-dose implant. Hence, a relatively high-energy low-dose implant of ions is performed into a source/drain region of a substrate. A diffusion retarding implant is performed into the source/drain region of the substrate. Then after performing the high-energy low-dose implant and the diffusion retarding implant (together, overlapping, or separately), a relatively low-energy high-dose implant of ions is performed into the source/drain region of the substrate.

    摘要翻译： 提供了一种制造集成电路芯片的方法，其将智能分级植入物与扩散延迟植入物组合，例如以改善短沟道效应可控性并改善源极/漏极区域中的掺杂剂分级。 使用智能分级植入物，在相对低能量的高剂量植入物之前进行相对低能量的高剂量种植体。 因此，相对高能量的低剂量离子注入被执行到衬底的源极/漏极区域中。 扩散阻滞注入被执行到衬底的源极/漏极区域中。 然后，在执行高能量低剂量注入和扩散阻滞植入（一起，重叠或分开））之后，将相对较低能量的高剂量离子注入进入衬底的源极/漏极区。

    High performance MOS device with graded silicide
    9.
    发明授权
    High performance MOS device with graded silicide 有权
    具有分级硅化物的高性能MOS器件

    公开(公告)号：US07253481B2

    公开(公告)日：2007-08-07

    申请号：US11181521

    申请日：2005-07-14

    申请人： Chih-Hao Wang ,  Ta-Wei Wang ,  Ching-Wei Tsai

    发明人： Chih-Hao Wang ,  Ta-Wei Wang ,  Ching-Wei Tsai

    IPC分类号： H01L29/772

    CPC分类号： H01L29/7843 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  Y10S257/90

    摘要： A semiconductor device suffering fewer current crowding effects and a method of forming the same are provided. The semiconductor device includes a substrate, a gate over the substrate, a gate spacer along an edge of the gate and overlying a portion of the substrate, a diffusion region in the substrate wherein the diffusion region comprises a first portion and a second portion between the first portion and the gate spacer. The first portion of the diffusion region has a recessed top surface. The semiconductor device further includes a silicide layer on the diffusion region, and a cap layer over at least the silicide layer. The cap layer provides a strain to the channel region of the semiconductor device.

    摘要翻译： 提供了具有较少的电流拥挤效应的半导体器件及其形成方法。 半导体器件包括衬底，衬底上的栅极，沿着栅极的边缘并覆盖衬底的一部分的栅极间隔区，衬底中的扩散区域，其中扩散区域包括第一部分和第二部分之间 第一部分和栅极间隔物。 扩散区域的第一部分具有凹入的顶表面。 半导体器件还包括在扩散区上的硅化物层，以及至少在硅化物层上的覆盖层。 盖层向半导体器件的沟道区域提供应变。