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    High voltage three-dimensional devices having dielectric liners
    1.
    发明授权
    High voltage three-dimensional devices having dielectric liners 有权
    具有电介质衬垫的高压三维器件

    公开(公告)号：US09570467B2

    公开(公告)日：2017-02-14

    申请号：US14641117

    申请日：2015-03-06

    申请人： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

    发明人： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

    IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

    CPC分类号： H01L27/1211 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

    摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

    摘要翻译： 描述了具有电介质衬垫的高压三维器件和形成具有电介质衬垫的高电压三维器件的方法。 例如，半导体结构包括设置在基板上方的第一鳍状物活性区域和第二鳍状物活性区域。 第一栅极结构设置在第一鳍片活动区域的顶表面之上并且沿着第一鳍片活动区域的侧壁的上方。 第一栅极结构包括第一栅极电介质，第一栅极电极和第一间隔物。 第一栅极电介质由设置在第一鳍状物活性区域上并沿着第一间隔物的侧壁的第一介电层和设置在第一介电层上并沿着第一间隔物的侧壁的第二不同介电层组成。 半导体结构还包括第二栅极结构，其设置在第二鳍片活动区域的顶表面之上并且沿着第二鳍片活动区域的侧壁的上方。 第二栅极结构包括第二栅极电介质，第二栅电极和第二间隔物。 第二栅极电介质由设置在第二鳍状物活性区域和第二间隔物的侧壁上的第二介电层构成。

    ANTIFUSE ELEMENT UTILIZING NON-PLANAR TOPOLOGY
    4.
    发明申请
    ANTIFUSE ELEMENT UTILIZING NON-PLANAR TOPOLOGY 有权
    使用非平面拓扑学的抗体元件

    公开(公告)号：US20130270559A1

    公开(公告)日：2013-10-17

    申请号：US13976087

    申请日：2011-10-18

    申请人： Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park ,  Jeng-Ya D. Yeh

    发明人： Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park ,  Jeng-Ya D. Yeh

    IPC分类号： H01L27/112

    CPC分类号： H01L27/11206 ,  H01L21/823821 ,  H01L23/5252 ,  H01L27/0924 ,  H01L29/7853 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In sonic embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.

    摘要翻译： 本文公开了用于提供非易失性反熔丝存储元件和其它反熔丝链路的技术。 在声音实施例中，反熔丝存储器元件被配置为具有诸如FinFET拓扑的非平面拓扑。 在一些这样的实施例中，可以通过产生适合用于较低电压非易失性反熔丝存储器元件的增强发射位点来操纵翅片拓扑并用于有效地促进较低击穿电压晶体管。 在一个示例实施例中，提供了一种半导体反熔丝装置，其包括具有锥形部分的翅片的非平面扩散区域，在包括锥形部分的鳍片上的介电隔离层和介电隔离层上的栅极材料。 翅片的锥形部分可以例如通过氧化，蚀刻和/或烧蚀形成，并且在一些情况下包括基底区域和变薄区域，并且变薄区域比基底区域薄至少50％ 。

    Precision resistor for non-planar semiconductor device architecture
    5.
    发明授权
    Precision resistor for non-planar semiconductor device architecture 有权
    用于非平面半导体器件结构的精密电阻器

    公开(公告)号：US08889508B2

    公开(公告)日：2014-11-18

    申请号：US14313678

    申请日：2014-06-24

    申请人： Jeng-Ya D. Yeh ,  Peter J. Vandervoorn ,  Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park

    发明人： Jeng-Ya D. Yeh ,  Peter J. Vandervoorn ,  Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park

    IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L49/02

    CPC分类号： H01L21/823431 ,  H01L27/0629 ,  H01L27/0886 ,  H01L28/20 ,  H01L29/66545 ,  H01L29/66795

    摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

    摘要翻译： 描述了用于非平面半导体器件结构的精密电阻器。 在第一示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。 电阻器结构设置在第一半导体鳍片上方，但不在第二半导体鳍片之上。 晶体管结构由第二半导体鳍形成，但不由第一半导体鳍形成。 在第二示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。 隔离区设置在基板之上，位于第一和第二半导体鳍之间，并且在小于第一和第二半导体鳍片的高度处。 电阻结构设置在隔离区域上方，但不在第一和第二半导体鳍片之上。 第一和第二晶体管结构分别由第一和第二半导体鳍形成。

    Antifuse element utilizing non-planar topology
    8.
    发明授权
    Antifuse element utilizing non-planar topology 有权
    使用非平面拓扑结构的消毒元件

    公开(公告)号：US09159734B2

    公开(公告)日：2015-10-13

    申请号：US13976087

    申请日：2011-10-18

    申请人： Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park ,  Jeng-Ya D. Yeh

    发明人： Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park ,  Jeng-Ya D. Yeh

    IPC分类号： H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L27/112 ,  H01L23/525 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

    CPC分类号： H01L27/11206 ,  H01L21/823821 ,  H01L23/5252 ,  H01L27/0924 ,  H01L29/7853 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.

    摘要翻译： 本文公开了用于提供非易失性反熔丝存储元件和其它反熔丝链路的技术。 在一些实施例中，反熔丝存储器元件被配置为非平面拓扑，例如FinFET拓扑。 在一些这样的实施例中，可以通过产生适合用于较低电压非易失性反熔丝存储器元件的增强发射位点来操纵翅片拓扑并用于有效地促进较低击穿电压晶体管。 在一个示例实施例中，提供了一种半导体反熔丝装置，其包括具有锥形部分的翅片的非平面扩散区域，在包括锥形部分的鳍片上的介电隔离层和介电隔离层上的栅极材料。 翅片的锥形部分可以例如通过氧化，蚀刻和/或烧蚀形成，并且在一些情况下包括基底区域和变薄区域，并且变薄区域比基底区域薄至少50％ 。

    TRANSISTOR ARCHITECTURE HAVING EXTENDED RECESSED SPACER AND SOURCE/DRAIN REGIONS AND METHOD OF MAKING SAME
    9.
    发明申请
    TRANSISTOR ARCHITECTURE HAVING EXTENDED RECESSED SPACER AND SOURCE/DRAIN REGIONS AND METHOD OF MAKING SAME 有权
    具有延伸的间隔器和源/排水区域的晶体管结构及其制造方法

    公开(公告)号：US20140291737A1

    公开(公告)日：2014-10-02

    申请号：US13995717

    申请日：2013-03-29

    申请人： Walid M. Hafez ,  Joodong Park ,  Jeng-Ya D. Yeh ,  Chia-Hong Jan ,  Curtis Tsai

    发明人： Walid M. Hafez ,  Joodong Park ,  Jeng-Ya D. Yeh ,  Chia-Hong Jan ,  Curtis Tsai

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/785 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78

    摘要： Techniques are disclosed for forming transistor architectures having extended recessed spacer and source/drain (S/D) regions. In some embodiments, a recess can be formed, for example, in the top of a fin of a fin-based field-effect transistor (finFET), such that the recess allows for forming extended recessed spacers and S/D regions in the finFET that are adjacent to the gate stack. In some instances, this configuration provides a higher resistance path in the top of the fin, which can reduce gate-induced drain leakage (GIDL) in the finFET. In some embodiments, precise tuning of the onset of GIDL can be provided. Some embodiments may provide a reduction in junction leakage (Lb) and a simultaneous increase in threshold voltage (VT). The disclosed techniques can be implemented with planar and non-planar fin-based architectures and can be used in standard metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) process flows, in some embodiments.

    摘要翻译： 公开了用于形成具有延伸的凹入间隔物和源极/漏极（S / D）区域的晶体管架构的技术。 在一些实施例中，可以例如在鳍式场效应晶体管（finFET）的鳍的顶部形成凹部，使得凹部允许在鳍状物FET中形成延伸的凹入的间隔物和S / D区域 它们与栅极堆叠相邻。 在一些情况下，该配置在鳍的顶部提供更高的电阻路径，这可以减少finFET中的栅极引起的漏极泄漏（GIDL）。 在一些实施例中，可以提供GIDL的开始的精确调整。 一些实施例可以提供结漏电（Lb）的降低和阈值电压（VT）的同时增加。 所公开的技术可以用平面和非平面鳍状结构来实现，并且在一些实施例中可以用于标准金属氧化物半导体（MOS）和互补MOS（CMOS）工艺流程中。