公开(公告)号：US08114715B2

公开(公告)日：2012-02-14

申请号：US12654810

申请日：2010-01-05

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/82

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

摘要翻译： 提供了包括绝缘层，硬掩模层，底电极，存储单元和顶电极的电阻随机存取存储器。 绝缘层设置在底部电极上。 绝缘层具有第一宽度的接触孔。 硬掩模层具有开口。 存储单元的一部分从开口露出并且具有小于第一宽度的第二宽度。 顶部电极设置在绝缘层上并与存储单元耦合。

公开(公告)号：US20090072211A1

公开(公告)日：2009-03-19

申请号：US11898529

申请日：2007-09-13

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L47/00 ,  H01L21/06

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

摘要翻译： 提供了包括绝缘层，硬掩模层，底电极，存储单元和顶电极的电阻随机存取存储器。 绝缘层设置在底部电极上。 绝缘层具有第一宽度的接触孔。 硬掩模层具有开口。 存储单元的一部分从开口露出并且具有小于第一宽度的第二宽度。 顶部电极设置在绝缘层上并与存储单元耦合。

公开(公告)号：US20110250729A1

公开(公告)日：2011-10-13

申请号：US13163769

申请日：2011-06-20

申请人： Erh-Kun Lai ,  Chia-Hua Ho ,  Kuang-Yeu Hsieh

发明人： Erh-Kun Lai ,  Chia-Hua Ho ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/20

CPC分类号： H01L27/24 ,  G11C11/5664 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0016 ,  G11C16/0475 ,  G11C2213/31 ,  G11C2213/51

摘要： A method for fabricating a memory is described. Word lines are provided in a first direction. Bit lines are provided in a second direction. A top electrode is formed connecting to a corresponding word line. A bottom electrode is formed connecting to a corresponding bit line. A resistive layer is formed on the bottom electrode. At least two separate L-shaped liners are formed, wherein each L-shaped liner has variable resistive materials on both ends of the L-shaped liner and each L-shaped liner is coupled between the top electrode and the resistive layer.

摘要翻译： 描述了一种制造存储器的方法。 字线在第一方向上提供。 位线沿第二方向设置。 形成连接到相应字线的顶部电极。 形成连接到相应位线的底部电极。 电阻层形成在底部电极上。 形成至少两个单独的L形衬垫，其中每个L形衬垫在L形衬套的两端具有可变电阻材料，并且每个L形衬垫耦合在顶部电极和电阻层之间。

公开(公告)号：US20100112810A1

公开(公告)日：2010-05-06

申请号：US12654810

申请日：2010-01-05

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/28

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

公开(公告)号：US20090166604A1

公开(公告)日：2009-07-02

申请号：US12403186

申请日：2009-03-12

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L27/24

CPC分类号： G11C11/54 ,  G11C11/14 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  Y10S438/972

摘要： A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer. The second resistivity is greater than the first resistivity, and the first resistivity is greater than the third resistivity.

摘要翻译： 提供电阻型存储器件。 电阻型存储器件包括第一和第二导体和金属氧化物层。 金属氧化物层设置在第一和第二导体之间，电阻型存储装置被定义为第一电阻率。 在向金属氧化物层施加第一脉冲电压之后，将电阻型存储器件定义为第二电阻率。 在向金属氧化物层施加第二脉冲电压之后，将电阻型存储器件定义为第三电阻率。 第二电阻率大于第一电阻率，第一电阻率大于第三电阻率。

公开(公告)号：US20080237798A1

公开(公告)日：2008-10-02

申请号：US11867000

申请日：2007-10-04

申请人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou Lee ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L27/101 ,  H01L28/20 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1675

摘要： A memory cell and a process for manufacturing the same are provided. In the process, a first electrode layer is formed on a conductive layer over a substrate, and then a transition metal layer is formed on the first electrode layer. After that, the transition metal layer is subjected to a plasma oxidation step to form a transition metal oxide layer as a precursor of a data storage layer, and a second electrode layer is formed on the transition metal oxide layer. A memory cell is formed after the second electrode layer, the transition metal oxide layer and the first electrode layer are patterned into a second electrode, a data storage layer and a first electrode, respectively.

摘要翻译： 提供了一种存储单元及其制造方法。 在该工艺中，在衬底上的导电层上形成第一电极层，然后在第一电极层上形成过渡金属层。 之后，对过渡金属层进行等离子体氧化工序，形成作为数据存储层的前体的过渡金属氧化物层，在过渡金属氧化物层上形成第二电极层。 在第二电极层，过渡金属氧化物层和第一电极层分别形成第二电极，数据存储层和第一电极之后形成存储单元。

公开(公告)号：US20060226467A1

公开(公告)日：2006-10-12

申请号：US11100518

申请日：2005-04-07

申请人： Hang-Ting Lue ,  Min-Ta Wu ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Chia-Hua Ho ,  Kuang-Yeu Hsieh

发明人： Hang-Ting Lue ,  Min-Ta Wu ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Chia-Hua Ho ,  Kuang-Yeu Hsieh

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0475 ,  H01L27/115 ,  H01L29/40117 ,  H01L29/4232 ,  H01L29/792

摘要： A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first inversion region, a second inversion region, and a channel region between the first inversion region and the second inversion region. The semiconductor device further includes a control gate over the channel region and at least one sub-gate over the first and second inversion regions, wherein the control gate does not extend over the at least one sub-gate.

摘要翻译： 半导体器件包括半导体衬底。 半导体衬底包括第一反转区域，第二反转区域和第一反转区域和第二反转区域之间的沟道区域。 所述半导体器件还包括在所述沟道区上的控制栅极以及所述第一和第二反转区域上的至少一个子栅极，其中所述控制栅极不在所述至少一个子栅极上延伸。

公开(公告)号：US20120108031A1

公开(公告)日：2012-05-03

申请号：US13346935

申请日：2012-01-10

申请人： Ming-Daou LEE ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Ming-Daou LEE ,  Chia-Hua Ho ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/02

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1633

摘要： A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell.

摘要翻译： 提供了包括绝缘层，硬掩模层，底电极，存储单元和顶电极的电阻随机存取存储器。 绝缘层设置在底部电极上。 绝缘层具有第一宽度的接触孔。 硬掩模层具有开口。 存储单元的一部分从开口露出并且具有小于第一宽度的第二宽度。 顶部电极设置在绝缘层上并与存储单元耦合。

公开(公告)号：US07973366B2

公开(公告)日：2011-07-05

申请号：US11352788

申请日：2006-02-13

申请人： Chia-Hua Ho ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Chia-Hua Ho ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L29/792

CPC分类号： H01L29/7923 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

摘要： Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate disposed above the charge-trapping structure and proximate to the drain region; where the first gate and the second gate are separated by a first nanospace are provided, along with arrays including a plurality of such cells, methods of manufacturing such cells and methods of operating such cells.

摘要翻译： 存储单元，其包括具有由沟道区域分离的源极区域和漏极区域的半导体衬底; 电荷捕获结构，设置在所述半导体衬底的沟道区之上; 设置在电荷捕获结构上方并靠近源极区的第一栅极; 以及第二栅极，其设置在所述电荷捕获结构的上方并且靠近所述漏极区; 提供了第一栅极和第二栅极被第一纳米级分隔开的区域，以及包括多个这样的电池的阵列，制造这种电池的方法以及操作这种电池的方法。

公开(公告)号：US07688615B2

公开(公告)日：2010-03-30

申请号：US11949814

申请日：2007-12-04

申请人： Chia-Hua Ho ,  Kuang-Yeu Hsieh

发明人： Chia-Hua Ho ,  Kuang-Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： H01L43/08 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/5607 ,  H01L27/222 ,  H01L43/12

摘要： A magnetic random access memory (MRAM) and a manufacturing method and a programming method thereof are provided. The magnetic random access memory comprises a first magnetic tunnel junction structure and a second magnetic tunnel junction structure. The second magnetic tunnel junction structure is electrically connected with the first magnetic tunnel junction structure, and the volume of the second magnetic tunnel junction structure is smaller than that of the first magnetic tunnel junction structure.

摘要翻译： 提供磁性随机存取存储器（MRAM）及其制造方法及其编程方法。 磁性随机存取存储器包括第一磁性隧道结结构和第二磁性隧道结结构。 第二磁性隧道结结构与第一磁性隧道结结构电连接，并且第二磁性隧道结结构的体积小于第一磁性隧道结结构的体积。