公开(公告)号：US20070004112A1

公开(公告)日：2007-01-04

申请号：US11161210

申请日：2005-07-27

申请人： Chia-Nan Shen ,  Cheng-Nan Hsieh ,  Hsi-Ming Chang

发明人： Chia-Nan Shen ,  Cheng-Nan Hsieh ,  Hsi-Ming Chang

IPC分类号： H01L21/8234

CPC分类号： H01L29/78675 ,  H01L29/66757

摘要： A method of forming a thin film transistor is described. A polysilicon layer is formed over a substrate, wherein the polysilicon layer has a first region, a second region and a channel region between the first and second regions. A nitrogen doping process is carried out to dope nitrogen into the polysilicin layer. A gate insulating layer and a gate are sequentially formed over the polysilicon layer, wherein the gate is formed over the channel region. A doping process is performed so as to form a source and a drain in the first region and second region, respectively.

摘要翻译： 描述形成薄膜晶体管的方法。 在衬底上形成多晶硅层，其中多晶硅层在第一和第二区域之间具有第一区域，第二区域和沟道区域。 进行氮掺杂工艺以将氮掺入聚硅酸层中。 栅极绝缘层和栅极依次形成在多晶硅层上，其中栅极形成在沟道区域上。 执行掺杂工艺以分别在第一区域和第二区域中形成源极和漏极。

公开(公告)号：US07041540B1

公开(公告)日：2006-05-09

申请号：US10906041

申请日：2005-02-01

申请人： Hsi-Ming Chang ,  Chia-Nan Shen

发明人： Hsi-Ming Chang ,  Chia-Nan Shen

IPC分类号： H01L21/84

CPC分类号： H01L29/66757 ,  H01L21/26513 ,  H01L29/78621 ,  H01L29/78624

摘要： A thin film transistor includes a substrate, a polysilicon layer, a patterned gate dielectric layer, a gate layer, a channel region, a source region, a drain region, and a LDD region. The polysilicon layer is positioned over the substrate. The patterned gate dielectric layer is positioned over the polysilicon layer. The patterned gate dielectric layer has a third and a fourth portion, wherein the fourth portion has a thickness smaller than that of the third portion. The gate layer is positioned over the third portion. The source region and the drain region are positioned in the polysilicon layer under the fourth portion. The channel region is positioned in the polysilicon layer under the gate layer. The LDD region is positioned in the polysilicon layer under the third portion and is between the channel region and the source region or between the channel region and the drain region.

摘要翻译： 薄膜晶体管包括衬底，多晶硅层，图案化栅极介电层，栅极层，沟道区，源极区，漏极区和LDD区。 多晶硅层位于衬底上。 图案化的栅介质层位于多晶硅层上。 图案化的栅介质层具有第三部分和第四部分，其中第四部分的厚度小于第三部分的厚度。 栅极层位于第三部分上。 源极区域和漏极区域位于第四部分下面的多晶硅层中。 沟道区位于栅极层下面的多晶硅层中。 LDD区域位于第三部分下面的多晶硅层中，并且位于沟道区域和源极区域之间或沟道区域和漏极区域之间。

公开(公告)号：US20060199337A1

公开(公告)日：2006-09-07

申请号：US11306898

申请日：2006-01-16

申请人： Hsi-Ming Chang ,  Chia-Nan Shen

发明人： Hsi-Ming Chang ,  Chia-Nan Shen

IPC分类号： H01L21/84 ,  H01L21/336 ,  H01L31/00

CPC分类号： H01L21/26513 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78624

摘要： A thin film transistor includes a substrate, a polysilicon layer, a patterned gate dielectric layer, a gate layer, a channel region, a source region, a drain region, and a LDD region. The polysilicon layer is positioned over the substrate. The patterned gate dielectric layer is positioned over the polysilicon layer. The patterned gate dielectric layer has a third and a fourth portion, wherein the fourth portion has a thickness smaller than that of the third portion. The gate layer is positioned over the third portion. The source region and the drain region are positioned in the polysilicon layer under the fourth portion. The channel region is positioned in the polysilicon layer under the gate layer. The LDD region is positioned in the polysilicon layer under the third portion and is between the channel region and the source region or between the channel region and the drain region.

摘要翻译： 薄膜晶体管包括衬底，多晶硅层，图案化栅极介电层，栅极层，沟道区，源极区，漏极区和LDD区。 多晶硅层位于衬底上。 图案化的栅介质层位于多晶硅层上。 图案化的栅介质层具有第三部分和第四部分，其中第四部分的厚度小于第三部分的厚度。 栅极层位于第三部分上。 源极区域和漏极区域位于第四部分下面的多晶硅层中。 沟道区位于栅极层下面的多晶硅层中。 LDD区域位于第三部分下面的多晶硅层中，并且位于沟道区域和源极区域之间或沟道区域和漏极区域之间。

公开(公告)号：US20150109769A1

公开(公告)日：2015-04-23

申请号：US14058292

申请日：2013-10-21

申请人： Hsi-Ming Chang

发明人： Hsi-Ming Chang

IPC分类号： F21L4/00

CPC分类号： F21V21/145 ,  A42B3/044

摘要： An angle-adjustable lighting device includes a mounting device including a mounting base formed integral with or affixed to a pair of goggles, engineering cap, face shield or headphone and a plurality of arched retaining bars equiangularly spaced around the periphery of the mounting base and obliquely forwardly extending in direction toward each other, and a lighting device including a battery-operated LED, a switch operable to turn on/off the battery-operated LED and a rod member located at one lateral side thereof and terminating in a coupling ball that is detachably coupled to the arched retaining bars of the mounting device.

摘要翻译： 角度可调的照明装置包括安装装置，该安装装置包括与一对护目镜，工程帽，面罩或耳机一体形成或固定在其上的安装基座，以及围绕安装基座的周边等角间隔开的多个拱形保持杆， 朝向彼此的方向向前延伸，以及包括电池供电的LED的照明装置，可操作以打开/关闭电池供电的LED的开关和位于其一个侧面的杆构件，并且终止于联接球 可拆卸地联接到安装装置的拱形保持杆。

公开(公告)号：US08664024B2

公开(公告)日：2014-03-04

申请号：US13471467

申请日：2012-05-15

申请人： Hsi-Ming Chang

发明人： Hsi-Ming Chang

IPC分类号： H01L21/00 ,  H01L33/00

CPC分类号： H01L27/1225 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/7869

摘要： A pixel structure and a fabrication method thereof are provided. A scan line, a gate, an oxide conductor layer, a metal conductor layer, an oxide semiconductor layer, and an insulation layer between the gate and the metal conductor layer are formed on a substrate. The oxide conductor layer includes a pixel electrode and a first auxiliary pattern partially overlapped with where the gate is. The first auxiliary pattern includes a first metal contact portion and a first semiconductor contact portion. The metal conductor layer includes a data line, a source connected to the data line, and a drain separated from the source. The drain contacts the first metal contact portion, exposes the first semiconductor contact portion between the source and the drain, and is electrically connected to the pixel electrode. The oxide semiconductor layer is connected between the source and the drain and contacts the first semiconductor contact portion.

摘要翻译： 提供了像素结构及其制造方法。 在基板上形成栅极和金属导体层之间的扫描线，栅极，氧化物导体层，金属导体层，氧化物半导体层以及绝缘层。 氧化物导体层包括像素电极和与栅极的部分重叠的第一辅助图案。 第一辅助图案包括第一金属接触部分和第一半导体接触部分。 金属导体层包括数据线，连接到数据线的源和与源分离的漏极。 漏极接触第一金属接触部分，暴露源极和漏极之间的第一半导体接触部分，并且电连接到像素电极。 氧化物半导体层连接在源极和漏极之间并与第一半导体接触部分接触。

公开(公告)号：US08461048B2

公开(公告)日：2013-06-11

申请号：US13034651

申请日：2011-02-24

申请人： Hsi-Ming Chang

发明人： Hsi-Ming Chang

IPC分类号： H01L21/311

CPC分类号： G02F1/13439 ,  G02F1/134363

摘要： A fabrication method of a minute pattern at least includes following steps. A first crystallizable material layer is formed on a base material. The first crystallizable material layer is patterned to form a plurality of first patterns on the base material. A distance between every two adjacent first patterns is greater than a width of each of the first patterns. A first treatment process is performed to crystallize the first patterns. A second crystallizable material layer is formed on the base material and covers the first patterns. The second crystallizable material layer is patterned to form a plurality of second patterns on the base material. Each of the second patterns is located between the first patterns adjacent thereto, respectively.

摘要翻译： 微小图案的制造方法至少包括以下步骤。 在基材上形成第一可结晶材料层。 将第一可结晶材料层图案化以在基材上形成多个第一图案。 每两个相邻的第一图案之间的距离大于每个第一图案的宽度。 执行第一处理过程以使第一图案结晶。 第二可结晶材料层形成在基材上并覆盖第一图案。 将第二可结晶材料层图案化以在基材上形成多个第二图案。 每个第二图案分别位于与其相邻的第一图案之间。

公开(公告)号：US20130134514A1

公开(公告)日：2013-05-30

申请号：US13366267

申请日：2012-02-04

申请人： Hsi-Ming Chang

发明人： Hsi-Ming Chang

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L29/78606 ,  H01L29/78633

摘要： A thin film transistor and a fabricating method thereof are provided. The thin film transistor includes a gate, a gate insulator, an oxide semiconductor layer, a source, a drain, and a light barrier. The gate insulator covers the gate. The oxide semiconductor layer is disposed on the gate insulator and located above the gate. The source and the drain are disposed on parts of the oxide semiconductor layer. The light barrier is located above the oxide semiconductor layer and includes a first insulator, an ultraviolet shielding layer, and a second insulator. The first insulator is disposed above the oxide semiconductor layer. The ultraviolet shielding layer is disposed on the first insulator. The second insulator is disposed on the ultraviolet shielding layer.

摘要翻译： 提供薄膜晶体管及其制造方法。 薄膜晶体管包括栅极，栅极绝缘体，氧化物半导体层，源极，漏极和光栅。 门绝缘体覆盖门。 氧化物半导体层设置在栅极绝缘体上并位于栅极上方。 源极和漏极设置在氧化物半导体层的部分上。 光栅位于氧化物半导体层的上方，并且包括第一绝缘体，紫外线屏蔽层和第二绝缘体。 第一绝缘体设置在氧化物半导体层的上方。 紫外线屏蔽层设置在第一绝缘体上。 第二绝缘体设置在紫外线屏蔽层上。

公开(公告)号：US08179506B2

公开(公告)日：2012-05-15

申请号：US12183056

申请日：2008-07-30

申请人： Hsi-Ming Chang

发明人： Hsi-Ming Chang

IPC分类号： G02F1/1335

CPC分类号： H01L27/1288 ,  G02F1/1333 ,  G02F1/133555 ,  H01L27/1214

摘要： A transparent conductive layer and a first conductive layer are formed. A first photoresist layer having a first part and a second part with different thicknesses is as a mask to remove a portion of the first conductive layers to form a composite gate, and expose the transparent conductive layer of the pixel transmissive area and a portion of the transparent conductive layer in the pixel reflective area. The first photoresist layer is removed. A gate insulating layer and a semiconductor layer are formed. A second photoresist layer having a third part and a fourth part with different thicknesses is taken as a mask to remove a portion of the semiconductor layer and the gate insulating layer to form a contact opening and a channel layer. The second photoresist layer is removed. A patterned second conductive layer comprising a drain, a source and a reflective pattern is formed.

摘要翻译： 形成透明导电层和第一导电层。 具有第一部分和第二部分具有不同厚度的第一光致抗蚀剂层作为掩模以去除部分第一导电层以形成复合栅极，并且暴露像素透射区域的透明导电层和 透明导电层。 去除第一光致抗蚀剂层。 形成栅极绝缘层和半导体层。 将具有不同厚度的第三部分和第四部分的第二光致抗蚀剂层作为掩模，以去除半导体层和栅极绝缘层的一部分以形成接触开口和沟道层。 去除第二光致抗蚀剂层。 形成包括漏极，源极和反射图案的图案化的第二导电层。

公开(公告)号：US20100244026A1

公开(公告)日：2010-09-30

申请号：US12488596

申请日：2009-06-22

申请人： Hsi-Ming Chang

发明人： Hsi-Ming Chang

IPC分类号： H01L23/48

CPC分类号： H01L22/32 ,  H01L23/4985 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00013 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599

摘要： An active device array substrate is provided. The active device array substrate includes an active matrix device, first bonding pads electrically connected to the active matrix device, second bonding pads electrically insulated from the first bonding pads, test bonding pads disposed between the first and the second bonding pads and separated from the second bonding pads, switch devices disposed between the test bonding pads and the first bonding pads and electrically connected to the test bonding pads, a test signal pad, a switch device control pad, and at least one driving chip electrically connected to the first bonding pads, the second bonding pads, and the test bonding pads. Each test bonding pad is corresponding to one of the second bonding pads. Both the test signal pad for inputting/outputting a test signal and the switch device control pad for turning on/off the switch devices are electrically connected to the switch devices.

摘要翻译： 提供有源器件阵列衬底。 有源器件阵列衬底包括有源矩阵器件，电连接到有源矩阵器件的第一接合焊盘，与第一接合焊盘电绝缘的第二接合焊盘，设置在第一和第二接合焊盘之间并与第二接合焊盘分离的测试接合焊盘 接合焊盘，设置在测试接合焊盘和第一接合焊盘之间并电连接到测试接合焊盘的开关设备，测试信号焊盘，开关设备控制焊盘和电连接到第一接合焊盘的至少一个驱动芯片， 第二接合焊盘和测试接合焊盘。 每个测试接合焊盘对应于第二接合焊盘之一。 用于输入/输出测试信号的测试信号焊盘和用于打开/关闭开关装置的开关装置控制板电连接到开关装置。

公开(公告)号：US20130228781A1

公开(公告)日：2013-09-05

申请号：US13471467

申请日：2012-05-15

申请人： Hsi-Ming Chang

发明人： Hsi-Ming Chang

IPC分类号： H01L29/786 ,  H01L21/20

CPC分类号： H01L27/1225 ,  H01L21/02554 ,  H01L21/02565 ,  H01L29/7869

摘要： A pixel structure and a fabrication method thereof are provided. A scan line, a gate, an oxide conductor layer, a metal conductor layer, an oxide semiconductor layer, and an insulation layer between the gate and the metal conductor layer are formed on a substrate. The oxide conductor layer includes a pixel electrode and a first auxiliary pattern partially overlapped with where the gate is. The first auxiliary pattern includes a first metal contact portion and a first semiconductor contact portion. The metal conductor layer includes a data line, a source connected to the data line, and a drain separated from the source. The drain contacts the first metal contact portion, exposes the first semiconductor contact portion between the source and the drain, and is electrically connected to the pixel electrode. The oxide semiconductor layer is connected between the source and the drain and contacts the first semiconductor contact portion.

摘要翻译： 提供了像素结构及其制造方法。 在基板上形成栅极和金属导体层之间的扫描线，栅极，氧化物导体层，金属导体层，氧化物半导体层以及绝缘层。 氧化物导体层包括像素电极和与栅极的部分重叠的第一辅助图案。 第一辅助图案包括第一金属接触部分和第一半导体接触部分。 金属导体层包括数据线，连接到数据线的源和与源分离的漏极。 漏极接触第一金属接触部分，暴露源极和漏极之间的第一半导体接触部分，并且电连接到像素电极。 氧化物半导体层连接在源极和漏极之间并与第一半导体接触部分接触。