公开(公告)号：US08754422B2

公开(公告)日：2014-06-17

申请号：US13503172

申请日：2010-10-19

申请人： Chiaki Kudou ,  Kenya Yamashita ,  Masahiko Niwayama

发明人： Chiaki Kudou ,  Kenya Yamashita ,  Masahiko Niwayama

IPC分类号： H01L29/78

CPC分类号： H01L29/7828 ,  H01L21/0465 ,  H01L21/0485 ,  H01L23/485 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/4933 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device 100 includes: a first silicon carbide layer 120 arranged on the principal surface of a semiconductor substrate 101; a first impurity region 103 of a first conductivity type arranged in the first silicon carbide layer; a body region 104 of a second conductivity type; a contact region 131 of the second conductivity type which is arranged at a position in the body region that is deeper than the first impurity region 103 and which contains an impurity of the second conductivity type at a higher concentration than the body region; a drift region 102 of the first conductivity type; and a first ohmic electrode 122 in ohmic contact with the first impurity region 103 and the contact region 131, wherein: a contact trench 121, which penetrates through the first impurity region 103, is provided in the first silicon carbide layer 120; and the first ohmic electrode 122 is arranged in the contact trench 121 and is in contact with the contact region 131 on at least a portion of a side wall lower portion 121cL and a bottom surface 121b of the contact trench.

摘要翻译： 半导体器件100包括：布置在半导体衬底101的主表面上的第一碳化硅层120; 布置在第一碳化硅层中的第一导电类型的第一杂质区域103; 第二导电类型的体区104; 所述第二导电类型的接触区域131布置在比所述第一杂质区域103更深的所述体区域中并且包含比所述体区域更高的浓度的所述第二导电类型的杂质的位置处; 第一导电类型的漂移区域102; 以及与第一杂质区域103和接触区域131欧姆接触的第一欧姆电极122，其中：穿过第一杂质区域103的接触沟槽121设置在第一碳化硅层120中; 并且第一欧姆电极122布置在接触沟槽121中并且在接触沟槽的侧壁下部121cL和底表面121b的至少一部分上与接触区域131接触。

公开(公告)号：US20120205670A1

公开(公告)日：2012-08-16

申请号：US13503172

申请日：2010-10-19

申请人： Chiaki Kudou ,  Kenya Yamashita ,  Masahiko Niwayama

发明人： Chiaki Kudou ,  Kenya Yamashita ,  Masahiko Niwayama

IPC分类号： H01L29/808 ,  H01L21/337

CPC分类号： H01L29/7828 ,  H01L21/0465 ,  H01L21/0485 ,  H01L23/485 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/4933 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device 100 includes: a first silicon carbide layer 120 arranged on the principal surface of a semiconductor substrate 101; a first impurity region 103 of a first conductivity type arranged in the first silicon carbide layer; a body region 104 of a second conductivity type; a contact region 131 of the second conductivity type which is arranged at a position in the body region that is deeper than the first impurity region 103 and which contains an impurity of the second conductivity type at a higher concentration than the body region; a drift region 102 of the first conductivity type; and a first ohmic electrode 122 in ohmic contact with the first impurity region 103 and the contact region 131, wherein: a contact trench 121, which penetrates through the first impurity region 103, is provided in the first silicon carbide layer 120; and the first ohmic electrode 122 is arranged in the contact trench 121 and is in contact with the contact region 131 on at least a portion of a side wall lower portion 121cL and a bottom surface 121b of the contact trench.

摘要翻译： 半导体器件100包括：布置在半导体衬底101的主表面上的第一碳化硅层120; 布置在第一碳化硅层中的第一导电类型的第一杂质区域103; 第二导电类型的体区104; 所述第二导电类型的接触区域131布置在比所述第一杂质区域103更深的所述体区域中并且包含比所述体区域更高的浓度的所述第二导电类型的杂质的位置处; 第一导电类型的漂移区域102; 以及与第一杂质区域103和接触区域131欧姆接触的第一欧姆电极122，其中：穿过第一杂质区域103的接触沟槽121设置在第一碳化硅层120中; 并且第一欧姆电极122布置在接触沟槽121中并且在接触沟槽的侧壁下部121cL和底表面121b的至少一部分上与接触区域131接触。

公开(公告)号：US08653535B2

公开(公告)日：2014-02-18

申请号：US13701016

申请日：2011-08-29

申请人： Chiaki Kudou ,  Masahiko Niwayama ,  Ryo Ikegami

发明人： Chiaki Kudou ,  Masahiko Niwayama ,  Ryo Ikegami

IPC分类号： H01L29/15

CPC分类号： H01L29/1608 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/45 ,  H01L29/4933 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7828

摘要： A semiconductor device according to the present invention includes a contact region 201 of a second conductivity type which is provided in a body region 104. The contact region 201 includes a first region 201a in contact with a first ohmic electrode 122 and a second region 201b located at a position deeper than that of the first region 201a and in contact with the body region 104. The first region 201a and the second region 201b each have at least one peak of impurity concentration. The peak of impurity concentration in the first region 201a has a higher value than that of the peak of impurity concentration in the second region 201b.

摘要翻译： 根据本发明的半导体器件包括设置在体区104中的第二导电类型的接触区域201.接触区域201包括与第一欧姆电极122接触的第一区域201a和位于第二区域201b的第二区域201b 在比第一区域201a更深的位置处并且与主体区域104接触。第一区域201a和第二区域201b各自具有至少一个杂质浓度峰。 第一区域201a中的杂质浓度的峰值比第二区域201b中的杂质浓度的峰值高。

公开(公告)号：US08686439B2

公开(公告)日：2014-04-01

申请号：US13816571

申请日：2012-06-25

申请人： Kunimasa Takahashi ,  Masahiko Niwayama ,  Masao Uchida ,  Chiaki Kudou

发明人： Kunimasa Takahashi ,  Masahiko Niwayama ,  Masao Uchida ,  Chiaki Kudou

IPC分类号： H01L31/0312

CPC分类号： H01L29/1608 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7828

摘要： This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface.

公开(公告)号：US20130082285A1

公开(公告)日：2013-04-04

申请号：US13701016

申请日：2011-08-29

申请人： Chiaki Kudou ,  Masahiko Niwayama ,  Ryo Ikegami

发明人： Chiaki Kudou ,  Masahiko Niwayama ,  Ryo Ikegami

IPC分类号： H01L29/16

CPC分类号： H01L29/1608 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/45 ,  H01L29/4933 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7828

摘要： A semiconductor device according to the present invention includes a contact region 201 of a second conductivity type which is provided in a body region 104. The contact region 201 includes a first region 201a in contact with a first ohmic electrode 122 and a second region 201b located at a position deeper than that of the first region 201a and in contact with the body region 104. The first region 201a and the second region 201b each have at least one peak of impurity concentration. The peak of impurity concentration in the first region 201a has a higher value than that of the peak of impurity concentration in the second region 201b.

摘要翻译： 根据本发明的半导体器件包括设置在体区104中的第二导电类型的接触区域201.接触区域201包括与第一欧姆电极122接触的第一区域201a和位于第二区域201b的第二区域201b 在比第一区域201a更深的位置处并且与主体区域104接触。第一区域201a和第二区域201b各自具有至少一个杂质浓度峰。 第一区域201a中的杂质浓度的峰值比第二区域201b中的杂质浓度的峰值高。

公开(公告)号：US20130140586A1

公开(公告)日：2013-06-06

申请号：US13816571

申请日：2012-06-25

申请人： Kunimasa Takahashi ,  Masahiko Niwayama ,  Masao Uchida ,  Chiaki Kudou

发明人： Kunimasa Takahashi ,  Masahiko Niwayama ,  Masao Uchida ,  Chiaki Kudou

IPC分类号： H01L29/16 ,  H01L29/66

CPC分类号： H01L29/1608 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7828

摘要： This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface.

摘要翻译： 该碳化硅半导体元件包括：位于第一导电类型的漂移层上的第二导电类型的体区; 位于身体区域上的第一导电类型的杂质区域; 穿过身体区域和杂质区域到达漂移层的沟槽; 布置在沟槽表面上的栅极绝缘膜; 以及设置在栅极绝缘膜上的栅电极。 沟槽的表面包括与第一侧表面相对的第一侧表面和第二侧表面。 第二导电类型的掺杂剂的浓度至少局部地位于位于第一侧表面旁边的身体区域的部分中，而不是位于第二侧表面旁边的身体区域的另一部分中。

公开(公告)号：US08530943B2

公开(公告)日：2013-09-10

申请号：US12997958

申请日：2009-08-20

申请人： Kenya Yamashita ,  Chiaki Kudou

发明人： Kenya Yamashita ,  Chiaki Kudou

IPC分类号： H01L29/66

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003

摘要： The semiconductor device includes: a substrate 2 and a drift layer 3a, which are made of a wide-bandgap semiconductor; a p-type well 4a and a first n-type doped region 5, which are defined in the drift layer; a source electrode 5, which is electrically connected to the first n-type doped region 5; a second n-type doped region 30 arranged between its own well 4a and an adjacent unit cell's well 4a; a gate insulating film 7b, which covers at least partially the first and second n-type doped regions and the well 4a; a gate electrode 8 arranged on the gate insulating film; and a third n-type doped region 31, which is arranged adjacent to the second n-type doped region so as to cover one of the vertices of the unit cell and which has a dopant concentration that is higher than the drift layer and lower than the second n-type doped region.

摘要翻译： 半导体器件包括：由宽带隙半导体制成的衬底2和漂移层3a; 在漂移层中限定的p型阱4a和第一n型掺杂区5; 与第一n型掺杂区域5电连接的源电极5; 布置在其自己的井4a和相邻的单元电池的阱4a之间的第二n型掺杂区域30; 栅极绝缘膜7b，其至少部分地覆盖第一和第二n型掺杂区域和阱4a; 布置在栅极绝缘膜上的栅电极8; 以及第三n型掺杂区域31，其被布置为与第二n型掺杂区域相邻以覆盖单位晶胞的顶点中的一个，并且其掺杂浓度高于漂移层且低于 第二n型掺杂区域。

公开(公告)号：US20110095305A1

公开(公告)日：2011-04-28

申请号：US12997958

申请日：2009-08-20

申请人： Kenya Yamashita ,  Chiaki Kudou

发明人： Kenya Yamashita ,  Chiaki Kudou

IPC分类号： H01L29/24

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003

摘要： The semiconductor device includes: a substrate 2 and a drift layer 3a, which are made of a wide-bandgap semiconductor; a p-type well 4a and a first n-type doped region 5, which are defined in the drift layer; a source electrode 5, which is electrically connected to the first n-type doped region 5; a second n-type doped region 30 arranged between its own well 4a and an adjacent unit cell's well 4a; a gate insulating film 7b, which covers at least partially the first and second n-type doped regions and the well 4a; a gate electrode 8 arranged on the gate insulating film; and a third n-type doped region 31, which is arranged adjacent to the second n-type doped region so as to cover one of the vertices of the unit cell and which has a dopant concentration that is higher than the drift layer and lower than the second n-type doped region.

摘要翻译： 半导体器件包括：由宽带隙半导体制成的衬底2和漂移层3a; 在漂移层中限定的p型阱4a和第一n型掺杂区5; 与第一n型掺杂区域5电连接的源电极5; 布置在其自己的井4a和相邻的单元电池的阱4a之间的第二n型掺杂区域30; 栅极绝缘膜7b，其至少部分地覆盖第一和第二n型掺杂区域和阱4a; 布置在栅极绝缘膜上的栅电极8; 以及第三n型掺杂区域31，其被布置为与第二n型掺杂区域相邻以覆盖单位晶胞的顶点中的一个，并且其掺杂浓度高于漂移层且低于 第二n型掺杂区域。

公开(公告)号：US08729608B2

公开(公告)日：2014-05-20

申请号：US13811584

申请日：2012-09-10

申请人： Chiaki Kudou

发明人： Chiaki Kudou

IPC分类号： H01L27/148 ,  H01L29/76 ,  H01L21/338 ,  H01L21/336

CPC分类号： H01L29/7827 ,  H01L21/049 ,  H01L29/045 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7397

摘要： A semiconductor device (100) includes a substrate (1) having a semiconductor layer (102); a trench (12) in the semiconductor layer (102); a gate insulating film (11) covering a periphery and an inner surface of the trench (12); a gate electrode (8) including a portion filling the trench (12) and a portion around the trench (12), and provided on the gate insulating film (11); an interlayer insulating film (13) on the gate electrode (8); and a hollow (50) above and around the trench (12), and between the gate electrode (8) and the gate insulating film (11). Above the trench (12), the hollow (50) protrudes inside the trench (12) from a plane extending from an upper surface of the gate insulating film (11) at a portion covering the side surface of the trench (12) with a flat shape.

摘要翻译： 半导体器件（100）包括具有半导体层（102）的衬底（1）; 半导体层（102）中的沟槽（12）; 覆盖所述沟槽（12）的周边和内表面的栅极绝缘膜（11）; 包括填充所述沟槽（12）的部分和围绕所述沟槽（12）的部分的栅极电极（8），并设置在所述栅极绝缘膜（11）上; 在栅电极（8）上的层间绝缘膜（13）; 和沟槽（12）上方和周围的中空（50），以及栅电极（8）和栅极绝缘膜（11）之间。 在沟槽（12）的上方，中空部（50）从覆盖该沟槽（12）的侧面的部分的从栅极绝缘膜（11）的上表面延伸的面向内突出， 平坦的形状。

公开(公告)号：US07718519B2

公开(公告)日：2010-05-18

申请号：US12302372

申请日：2008-03-27

申请人： Kunimasa Takahashi ,  Chiaki Kudou

发明人： Kunimasa Takahashi ,  Chiaki Kudou

IPC分类号： H01L21/265

CPC分类号： H01L29/7802 ,  H01L21/046 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068

摘要： A method of producing a silicon carbide semiconductor device, including: step (A) of forming an impurity-doped region by implanting impurity ions 3 into at least a portion of a silicon carbide layer 2 formed on a first principal face of a silicon carbide substrate 1 having first and second principal faces; step (B) of forming capping layers 6 having thermal resistance on at least an upper face 2a of the silicon carbide layer 2 and on at least a second principal face 12a of the silicon carbide substrate 1; and step (C) of performing an activation annealing treatment by heating the silicon carbide layer 2 at a predetermined temperature.

摘要翻译： 一种制造碳化硅半导体器件的方法，包括：通过将杂质离子3注入形成在碳化硅衬底的第一主面上的碳化硅层2的至少一部分中来形成杂质掺杂区域的步骤（A） 1具有第一和第二主面; 在至少在碳化硅层2的上表面2a上形成具有耐热性的覆盖层6和在碳化硅衬底1的至少第二主面12a上的步骤（B）; 以及通过在预定温度下加热碳化硅层2进行活化退火处理的步骤（C）。