公开(公告)号：US08877623B2

公开(公告)日：2014-11-04

申请号：US13471128

申请日：2012-05-14

Applicant: Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L21/3205

CPC classification number: H01L29/6681 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/283 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

Abstract translation: 提供一种形成半导体器件的方法。 通过在衬底上的沉积工艺形成第一界面材料层。 在第一界面材料层上形成虚拟栅极材料层。 将虚拟栅材料层和第一界面材料层图案化以形成堆叠结构。 形成层间电介质（ILD）层以覆盖层叠结构。 去除ILD层的一部分以露出堆叠结构的顶部。 去除层叠结构以在ILD层中形成沟槽。 至少在沟槽的表面上共形地形成第二界面层和第一高k层。 复合金属层形成为至少填充沟槽。

公开(公告)号：US20140035066A1

公开(公告)日：2014-02-06

申请号：US13562322

申请日：2012-07-31

Applicant: Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Ying-Chih Lin ,  Chien-Ting Lin ,  Hsuan-Hsu Chen

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Ying-Chih Lin ,  Chien-Ting Lin ,  Hsuan-Hsu Chen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/51 ,  H01L29/66818 ,  H01L29/785

Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供一种非平面FET，其包括基板，鳍结构，子间隔物，栅极，电介质层和源极/漏极区域。 翅片结构设置在基板上。 子间隔件仅设置在翅片结构的中间侧壁上。 门设置在翅片结构上。 介电层设置在翅片结构和栅极之间。 源/漏区设置在鳍结构中。 本发明还提供一种形成该方法的方法。

公开(公告)号：US20130203230A1

公开(公告)日：2013-08-08

申请号：US13367376

申请日：2012-02-07

Applicant: Ying-Tsung Chen ,  Chien-Ting Lin ,  Ssu-I Fu ,  Shih-Hung Tsai ,  Wen-Tai Chiang ,  Chih-Wei Chen ,  Chiu-Hsien Yeh ,  Shao-Wei Wang ,  Kai-Ping Wang

Inventor： Ying-Tsung Chen ,  Chien-Ting Lin ,  Ssu-I Fu ,  Shih-Hung Tsai ,  Wen-Tai Chiang ,  Chih-Wei Chen ,  Chiu-Hsien Yeh ,  Shao-Wei Wang ,  Kai-Ping Wang

IPC: H01L21/336

CPC classification number: H01L29/66477 ,  H01L21/28185 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/7833

Abstract: A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer.

Abstract translation: 半导体工艺包括以下步骤。 提供基板。 进行臭氧饱和去离子水处理以在衬底上形成氧化物层。 在氧化物层上形成介电层。 在电介质层和氧化物层上进行后介电退火（PDA）工艺。

公开(公告)号：US20130154012A1

公开(公告)日：2013-06-20

申请号：US13326342

申请日：2011-12-15

Applicant: Ssu-I Fu ,  Wen-Tai Chiang ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Chi-Mao Hsu ,  Chin-Fu Lin

Inventor： Ssu-I Fu ,  Wen-Tai Chiang ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Chi-Mao Hsu ,  Chin-Fu Lin

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L21/28114 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.

Abstract translation: 具有金属栅极的半导体器件的制造方法包括提供具有第一半导体器件和形成在其上的第二半导体器件的衬底，所述第一半导体器件具有第一栅极沟槽，所述第二半导体器件具有第二栅极沟槽; 在基板上依次形成高介电常数（高k）栅介质层和多金属层; 在所述第一栅极沟槽中形成第一功函数金属层; 执行第一拉回步骤以从所述第一栅极沟槽去除所述第一功函数金属层的一部分; 在所述第一栅极沟槽和所述第二栅极沟槽中形成第二功函数金属层; 以及执行第二拉回步骤以从所述第一栅极沟槽和所述第二栅极沟槽去除所述第二功函数金属层的一部分。

公开(公告)号：US08470714B1

公开(公告)日：2013-06-25

申请号：US13477079

申请日：2012-05-22

Applicant: Shih-Hung Tsai ,  Ssu-I Fu ,  Chien-Liang Lin ,  Ying-Tsung Chen ,  Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chien-Ting Lin ,  Wen-Tai Chiang

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Chien-Liang Lin ,  Ying-Tsung Chen ,  Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L21/311

CPC classification number: H01L29/7854 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/66795

Abstract: A method of forming fin structure in integrated circuit comprising the steps of forming a plurality of fin structures on a substrate, covering an insulating layer on said substrate, performing a planarization process to expose mask layers, performing a wet etching process to etch said insulating layer, thereby exposing a part of the sidewall of said mask layer, removing said mask layer, and performing a dry etching process to remove pad layer and a part of said insulating layer, thereby exposing the top surface and a part of sidewall of said fin structures.

Abstract translation: 一种在集成电路中形成鳍结构的方法，包括以下步骤：在衬底上形成多个翅片结构，覆盖所述衬底上的绝缘层，执行平坦化处理以曝光掩模层，执行湿蚀刻工艺以蚀刻所述绝缘层 从而暴露所述掩模层的侧壁的一部分，去除所述掩模层，并进行干蚀刻工艺以去除衬垫层和所述绝缘层的一部分，从而暴露所述鳍结构的顶表面和侧壁的一部分 。

公开(公告)号：US08987096B2

公开(公告)日：2015-03-24

申请号：US13367376

申请日：2012-02-07

Applicant: Ying-Tsung Chen ,  Chien-Ting Lin ,  Ssu-I Fu ,  Shih-Hung Tsai ,  Wen-Tai Chiang ,  Chih-Wei Chen ,  Chiu-Hsien Yeh ,  Shao-Wei Wang ,  Kai-Ping Wang

Inventor： Ying-Tsung Chen ,  Chien-Ting Lin ,  Ssu-I Fu ,  Shih-Hung Tsai ,  Wen-Tai Chiang ,  Chih-Wei Chen ,  Chiu-Hsien Yeh ,  Shao-Wei Wang ,  Kai-Ping Wang

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/66477 ,  H01L21/28185 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/7833

Abstract: A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer.

Abstract translation: 半导体工艺包括以下步骤。 提供基板。 进行臭氧饱和去离子水处理以在衬底上形成氧化物层。 在氧化物层上形成介电层。 在电介质层和氧化物层上进行后介电退火（PDA）工艺。

公开(公告)号：US20130302976A1

公开(公告)日：2013-11-14

申请号：US13471128

申请日：2012-05-14

Applicant: Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L21/283

CPC classification number: H01L29/6681 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/283 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

Abstract translation: 提供一种形成半导体器件的方法。 通过在衬底上的沉积工艺形成第一界面材料层。 在第一界面材料层上形成虚拟栅极材料层。 将虚拟栅材料层和第一界面材料层图案化以形成堆叠结构。 形成层间电介质（ILD）层以覆盖层叠结构。 去除ILD层的一部分以露出堆叠结构的顶部。 去除层叠结构以在ILD层中形成沟槽。 至少在沟槽的表面上共形地形成第二界面层和第一高k层。 复合金属层形成为至少填充沟槽。

公开(公告)号：US08278184B1

公开(公告)日：2012-10-02

申请号：US13287131

申请日：2011-11-02

Applicant: Ying-Tsung Chen ,  Chien-Ting Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Wen-Tai Chiang

Inventor： Ying-Tsung Chen ,  Chien-Ting Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Wen-Tai Chiang

IPC: H01L21/76

CPC classification number: H01L21/324 ,  H01L21/76224 ,  H01L21/823431

Abstract: A method of forming a non-planar transistor is provided. A substrate is provided. The substrate has a plurality of isolation regions to be formed and a plurality of fin regions to be formed. A first etching process is performed to form a plurality of first trenches having a first depth in the substrate within the isolation regions. At least a doping region is formed in the substrate within the fin regions. A second etching process is performed to deepen the first depth to a second depth and a plurality of fin structures are formed in the substrate within the fin regions. Lastly, a gate is formed on the fin structures.

Abstract translation: 提供了一种形成非平面晶体管的方法。 提供基板。 基板具有要形成的多个隔离区域和要形成的多个翅片区域。 执行第一蚀刻工艺以形成在隔离区域内的衬底中具有第一深度的多个第一沟槽。 至少在鳍片区域内的衬底中形成掺杂区域。 执行第二蚀刻处理以将第一深度加深到第二深度，并且在鳍片区域内的衬底中形成多个鳍结构。 最后，在翅片结构上形成一个浇口。

公开(公告)号：US20130237046A1

公开(公告)日：2013-09-12

申请号：US13415855

申请日：2012-03-09

Applicant: Chien-Ting Lin ,  Ssu-I Fu

Inventor： Chien-Ting Lin ,  Ssu-I Fu

IPC: H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/823462 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

Abstract: A semiconductor process includes the following steps. A substrate having a first area and a second area is provided. A thick oxide layer and a dummy gate layer are formed on the substrate and in the first area and the second area. The dummy gate layer is removed to expose the thick oxide layer. The thick oxide layer in the first area is removed and then a thinner oxide layer is formed in the first area; or, the thick oxide layer in the first area is thinned down and a thinner oxide layer is therefore formed.

Abstract translation: 半导体工艺包括以下步骤。 提供具有第一区域和第二区域的衬底。 在基板上和第一区域和第二区域中形成厚的氧化物层和伪栅极层。 去除伪栅极层以暴露厚的氧化物层。 去除第一区域中的厚氧化物层，然后在第一区域中形成更薄的氧化物层; 或者，第一区域中的厚氧化物层变薄，因此形成较薄的氧化物层。

公开(公告)号：US20130200470A1

公开(公告)日：2013-08-08

申请号：US13367382

申请日：2012-02-07

Applicant: An-Chi Liu ,  Chun-Hsien Lin ,  Yu-Cheng Tung ,  Chien-Ting Lin ,  Wen-Tai Chiang ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen

Inventor： An-Chi Liu ,  Chun-Hsien Lin ,  Yu-Cheng Tung ,  Chien-Ting Lin ,  Wen-Tai Chiang ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7834 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

Abstract: A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.

Abstract translation: 一种半导体结构及其制造方法，包括以下步骤：提供衬底，在所述衬底上形成至少一个鳍结构，形成覆盖所述鳍结构的栅极，形成覆盖所述鳍结构的多个外延结构， 拉回过程以减小所述栅极的临界尺寸（CD）并分离所述栅极和所述外延结构，在所述鳍结构中形成轻掺杂的漏极（LDD），以及在所述栅极和所述鳍结构上形成间隔物。