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    INTERCONNECT STRUCTURE WITH IMPROVED ELECTROMIGRATION RESISTANCE AND METHOD OF FABRICATING SAME
    1.
    发明申请
    INTERCONNECT STRUCTURE WITH IMPROVED ELECTROMIGRATION RESISTANCE AND METHOD OF FABRICATING SAME 审中-公开
    具有改进的电阻率的互连结构及其制造方法

    公开(公告)号：US20090072406A1

    公开(公告)日：2009-03-19

    申请号：US11856970

    申请日：2007-09-18

    申请人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Kaushik Chanda

    发明人： Chih-Chao Yang ,  Ping-Chuan Wang ,  Kaushik Chanda

    IPC分类号： H01L21/31

    CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure in which the electromigration resistance thereof is improved without introducing a gouging feature within the interconnect structure is provided. The interconnect structure includes a metallic interfacial layer that is at least horizontally present at the bottom of an opening located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer does not form an alloy with an underlying conductive material that is embedded within the first dielectric material. In some embodiments of the present invention, the metallic interfacial layer is also present on exposed sidewalls of the second dielectric material that is located atop the first dielectric material. Atop the metallic interfacial layer there is present a diffusion barrier liner. In some embodiments, the diffusion barrier liner includes a lower layer of a metallic nitride and an upper layer of a metal. In accordance with the present invention, the metallic interfacial layer also does not form an alloy with any portion of the diffusion barrier liner.

    摘要翻译： 提供了一种互连结构，其中在不引入互连结构内的气蚀特征的情况下，其电迁移阻力得到改善。 互连结构包括金属界面层，其至少水平存在于位于第二介电材料内的开口的底部，该第二电介质材料位于第一电介质材料的顶部，该第一介电材料包括嵌入其中的第一导电材料。 金属界面层不与嵌入在第一介电材料内的下面的导电材料形成合金。 在本发明的一些实施例中，金属界面层也存在于位于第一介电材料顶部的第二介电材料的暴露的侧壁上。 在金属界面层顶部存在扩散阻挡层。 在一些实施例中，扩散阻挡衬里包括金属氮化物的下层和金属的上层。 根据本发明，金属界面层也不与扩散阻挡衬里的任何部分形成合金。

    SEMICONDUCTOR WIRING STRUCTURES INCLUDING DIELECTRIC CAP WITHIN METAL CAP LAYER
    2.
    发明申请
    SEMICONDUCTOR WIRING STRUCTURES INCLUDING DIELECTRIC CAP WITHIN METAL CAP LAYER 有权
    半导体接线结构包括金属盖层中的电介质盖

    公开(公告)号：US20080308942A1

    公开(公告)日：2008-12-18

    申请号：US11761495

    申请日：2007-06-12

    申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang ,  Chih-Chao Yang

    发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang ,  Chih-Chao Yang

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76865 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased.

    摘要翻译： 包括其中具有金属布线的电介质层，从金属布线向下延伸的孔，在金属布线上方的金属盖层和位于金属盖层的一部分内的局部电介质盖的半导体布线结构 公开了与金属布线的接触和相关方法。 局部电介质盖表示在双镶嵌互连的金属布线中有意创造的弱点，其在管线中引起电迁移（EM）空隙，而不是在从金属布线向下延伸的通孔的底部。 由于线路中的临界空隙尺寸失效，特别是金属盖层（衬垫）冗余度，远远大于通孔失效，所以EM寿命可以显着提高。

    Interconnect structure with bi-layer metal cap
    3.
    发明授权
    Interconnect structure with bi-layer metal cap 失效
    互连结构与双层金属盖

    公开(公告)号：US07745282B2

    公开(公告)日：2010-06-29

    申请号：US11675705

    申请日：2007-02-16

    申请人： Chih-Chao Yang ,  Kaushik Chanda ,  Ping-Chuan Wang

    发明人： Chih-Chao Yang ,  Kaushik Chanda ,  Ping-Chuan Wang

    IPC分类号： H01L21/8242 ,  H01L21/4763 ,  H01L21/22 ,  H01L21/38

    CPC分类号： H01L21/76849 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76856 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure and method of fabricating an interconnect structures with bi-layer metal cap is provided. In one embodiment, the method includes forming an interconnect feature in a dielectric material layer; and forming a bi-layer metallic cap on a top surface of the interconnect feature. The method further includes depositing a blanket layer of a dielectric capping layer, wherein the depositing covers an exposed surface of the dielectric material layer and a surface of the bi-layer metallic cap. The bi-layer metallic cap includes a metal capping layer formed on a conductive surface of the interconnect feature; and a metal nitride formed on a top portion of the metal capping layer. An interconnect structure is also described having an interconnect feature formed in a dielectric layer; a bi-layer metallic cap formed on a top portion of the interconnect feature; and a dielectric capping layer formed over the bi-layer metallic cap.

    摘要翻译： 提供了制造具有双层金属盖的互连结构的结构和方法。 在一个实施例中，该方法包括在电介质材料层中形成互连特征; 以及在所述互连特征的顶表面上形成双层金属帽。 该方法还包括沉积介电覆盖层的覆盖层，其中沉积覆盖电介质材料层的暴露表面和双层金属帽的表面。 双层金属盖包括形成在互连特征的导电表面上的金属覆盖层; 以及形成在金属覆盖层的顶部上的金属氮化物。 还描述了具有形成在电介质层中的互连特征的互连结构; 形成在互连特征的顶部上的双层金属帽; 以及形成在双层金属盖上的电介质覆盖层。

    Stress locking layer for reliable metallization
    4.
    发明授权
    Stress locking layer for reliable metallization 失效
    应力锁定层可靠的金属化

    公开(公告)号：US08420537B2

    公开(公告)日：2013-04-16

    申请号：US12127878

    申请日：2008-05-28

    申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Charles C. Goldsmith ,  Ping-Chuan Wang ,  Chih-Chao Yang

    发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Charles C. Goldsmith ,  Ping-Chuan Wang ,  Chih-Chao Yang

    IPC分类号： H01L21/302 ,  B44C1/22

    CPC分类号： H01L21/76877 ,  H01L21/76883

    摘要： Recrystallization and grain growth of metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 400° C., for example, for short anneal times of five to sixty minutes by forming a metal stress locking layer on the Cu before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the Cu by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing leaving the Cu interconnect with low stress and improved grain size and texture.

    摘要翻译： 在150℃至400℃的较高退火温度下实现诸如Cu的金属的重结晶和晶粒生长，例如，通过在Cu上形成金属应力锁定层，例如在短至五至六十分钟的短退火时间 在退火和化学机械抛光之前。 应力锁定层通过将原子扩散抑制到自由表面而延伸Cu的弹性区域，导致退火后在室温下拉伸应力接近零。 从而避免了造成可靠性问题的应力消除。 也实现了改善的晶粒尺寸和纹理。 通过化学机械抛光退火后去除应力锁定层，使Cu互连具有低应力和改善的晶粒尺寸和纹理。

    Semiconductor wiring structures including dielectric cap within metal cap layer
    5.
    发明授权
    Semiconductor wiring structures including dielectric cap within metal cap layer 有权
    包括金属盖层内的电介质盖的半导体布线结构

    公开(公告)号：US07732924B2

    公开(公告)日：2010-06-08

    申请号：US11761495

    申请日：2007-06-12

    申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang ,  Chih-Chao Yang

    发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang ,  Chih-Chao Yang

    IPC分类号： H01L23/52

    CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76865 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor wiring structures including a dielectric layer having a metal wiring line therein, a via extending downwardly from the metal wiring line, a metal cap layer over the metal wiring line, and a local dielectric cap positioned within a portion of the metal cap layer and in contact with the metal wiring line and a related method are disclosed. The local dielectric cap represents an intentionally created weak point in the metal wiring line of a dual-damascene interconnect, which induces electromigration (EM) voiding in the line, rather than at the bottom of a via extending downwardly from the metal wiring line. Since the critical void size in line fails, especially with metal cap layer (liner) redundancy, is much larger than that in via fails, the EM lifetime can be significantly increased.

    摘要翻译： 包括其中具有金属布线的电介质层，从金属布线向下延伸的孔，在金属布线上方的金属盖层和位于金属盖层的一部分内的局部电介质盖的半导体布线结构 公开了与金属布线的接触和相关方法。 局部电介质盖表示在双镶嵌互连的金属布线中有意创造的弱点，其在管线中引起电迁移（EM）空隙，而不是在从金属布线向下延伸的通孔的底部。 由于线路中的临界空隙尺寸失效，特别是金属盖层（衬垫）冗余度，远远大于通孔失效，所以EM寿命可以显着提高。

    Stress Locking Layer for Reliable Metallization
    6.
    发明申请
    Stress Locking Layer for Reliable Metallization 失效
    应力锁定层可靠金属化

    公开(公告)号：US20090297759A1

    公开(公告)日：2009-12-03

    申请号：US12127878

    申请日：2008-05-28

    申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Charles C. Goldsmith ,  Ping-Chuan Wang ,  Chih-Chao Yang

    发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Charles C. Goldsmith ,  Ping-Chuan Wang ,  Chih-Chao Yang

    IPC分类号： B05D5/12 ,  B32B3/02

    CPC分类号： H01L21/76877 ,  H01L21/76883

    摘要： Recrystallization and grain growth of metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 400° C., for example, for short anneal times of five to sixty minutes by forming a metal stress locking layer on the Cu before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the Cu by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing leaving the Cu interconnect with low stress and improved grain size and texture.

    摘要翻译： 在150℃至400℃的较高退火温度下实现诸如Cu的金属的重结晶和晶粒生长，例如，通过在Cu上形成金属应力锁定层，例如在短至五至六十分钟的短退火时间 在退火和化学机械抛光之前。 应力锁定层通过将原子扩散抑制到自由表面而延伸Cu的弹性区域，导致退火后在室温下拉伸应力接近零。 从而避免了造成可靠性问题的应力消除。 也实现了改善的晶粒尺寸和纹理。 通过化学机械抛光退火后去除应力锁定层，使Cu互连具有低应力和改善的晶粒尺寸和纹理。

    INTERCONNECT STRUCTURE WITH BI-LAYER METAL CAP
    7.
    发明申请
    INTERCONNECT STRUCTURE WITH BI-LAYER METAL CAP 失效
    具有双层金属盖的互连结构

    公开(公告)号：US20080197500A1

    公开(公告)日：2008-08-21

    申请号：US11675705

    申请日：2007-02-16

    申请人： Chih-Chao Yang ,  Kaushik Chanda ,  Ping-Chuan Wang

    发明人： Chih-Chao Yang ,  Kaushik Chanda ,  Ping-Chuan Wang

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L21/76849 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76856 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure and method of fabricating an interconnect structures with bi-layer metal cap is provided. In one embodiment, the method includes forming an interconnect feature in a dielectric material layer; and forming a bi-layer metallic cap on a top surface of the interconnect feature. The method further includes depositing a blanket layer of a dielectric capping layer, wherein the depositing covers an exposed surface of the dielectric material layer and a surface of the bi-layer metallic cap. The bi-layer metallic cap includes a metal capping layer formed on a conductive surface of the interconnect feature; and a metal nitride formed on a top portion of the metal capping layer. An interconnect structure is also described having an interconnect feature formed in a dielectric layer; a bi-layer metallic cap formed on a top portion of the interconnect feature; and a dielectric capping layer formed over the bi-layer metallic cap.

    摘要翻译： 提供了制造具有双层金属盖的互连结构的结构和方法。 在一个实施例中，该方法包括在电介质材料层中形成互连特征; 以及在所述互连特征的顶表面上形成双层金属帽。 该方法还包括沉积介电覆盖层的覆盖层，其中沉积覆盖电介质材料层的暴露表面和双层金属帽的表面。 双层金属盖包括形成在互连特征的导电表面上的金属覆盖层; 以及形成在金属覆盖层的顶部上的金属氮化物。 还描述了具有形成在电介质层中的互连特征的互连结构; 形成在互连特征的顶部上的双层金属帽; 以及形成在双层金属盖上的电介质覆盖层。