公开(公告)号：US06440861B1

公开(公告)日：2002-08-27

申请号：US09652471

申请日：2000-08-31

申请人： Chih-Chien Liu ,  Jui-Tsen Huang ,  Yi-Fang Cheng ,  Ming-Sheng Yang

发明人： Chih-Chien Liu ,  Jui-Tsen Huang ,  Yi-Fang Cheng ,  Ming-Sheng Yang

IPC分类号： H01L21302

CPC分类号： H01L21/76835 ,  H01L21/76808 ,  H01L2221/1063

摘要： A method of forming a dual damascene structure. A first dielectric layer and a second dielectric layer are sequentially formed over a substrate. A first photoresist layer is formed over the second dielectric layer. Photolithographic and etching operations are conducted to remove a portion of the second dielectric layer and the first dielectric layer so that a via opening is formed. A conformal third dielectric layer is coated over the surface of the second dielectric layer and the interior surface of the via opening. The conformal third dielectric layer forms a liner dielectric layer. A second photoresist layer is formed over the second dielectric layer and then the second photoresist layer is patterned. Using the patterned second photoresist layer as a mask, a portion of the second dielectric layer is removed to form a trench. The patterned second photoresist layer is removed. Conductive material is deposited over the substrate to fill the via opening and the trench. Finally, chemical-mechanical polishing is conducted to remove excess conductive material above the second dielectric layer.

摘要翻译： 形成双镶嵌结构的方法。 第一电介质层和第二电介质层依次形成在衬底上。 在第二介电层上形成第一光致抗蚀剂层。 进行光刻和蚀刻操作以去除第二介电层和第一介电层的一部分，从而形成通孔。 保形第三电介质层涂覆在第二电介质层的表面和通孔开口的内表面上。 保形第三电介质层形成衬里电介质层。 在第二电介质层上形成第二光致抗蚀剂层，然后对第二光致抗蚀剂层进行图案化。 使用图案化的第二光致抗蚀剂层作为掩模，去除第二介电层的一部分以形成沟槽。 去除图案化的第二光致抗蚀剂层。 导电材料沉积在衬底上以填充通孔和沟槽。 最后，进行化学机械抛光以除去第二介电层上方的多余的导电材料。

公开(公告)号：US06200653B1

公开(公告)日：2001-03-13

申请号：US09471055

申请日：1999-12-22

申请人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Ming-Sheng Yang

发明人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Ming-Sheng Yang

IPC分类号： H05H124

CPC分类号： H01L21/02131 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31053 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76829

摘要： A method is used to form an intermetal dielectric layer. According to the invention, an unbiased-unclamped fluorinated silicate glass layer used as a protection layer is formed by high density plasma chemical vapor deposition on a biased-clamped fluorinated silicate glass layer formed by high density plasma chemical vapor deposition to prevent the biased-clamped fluorinated silicate glass layer from being exposed in a planarization process.

公开(公告)号：US06197681B1

公开(公告)日：2001-03-06

申请号：US09477111

申请日：1999-12-31

申请人： Chih-Chien Liu ,  Cheng-Yuan Tsai ,  Ming-Sheng Yang

发明人： Chih-Chien Liu ,  Cheng-Yuan Tsai ,  Ming-Sheng Yang

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/76811

摘要： A method for forming the copper interconnects is disclosed. The method includes, firstly, providing a semiconductor substrate is provided. Then, a first dielectric layer is formed. Sequentially, a second dielectric layer is formed and an anti-reflective layer is formed. Then, a hardmask layer is formed. Etching of the hardmask layer is carried out. The photoresist layer is removed and another photoresist is replaced. The anti-reflective layer, the second dielectric layer and the first dielectric layer are all etched. The hardmask layer, the anti-reflective layer and the second dielectric layer are all etched. The photoresist layer, the hardmask layer and the anti-reflective layer are all removed. A first barrier layer is conformably formed on the sidewalls and the exposed surfaces of the second dielectric layer and the first dielectric layer, and on the surface of the first copper layer. A seed layer is conformably formed on the barrier layer. The via opening is filled up and the line opening with a second copper layer. Finally, the second copper layer can be planarized until the second dielectric layer is exposed.

摘要翻译： 公开了一种用于形成铜互连的方法。 该方法包括：首先提供半导体衬底。 然后，形成第一电介质层。 接着，形成第二电介质层，形成抗反射层。 然后，形成硬掩模层。 执行硬掩模层的蚀刻。 去除光致抗蚀剂层并替换另一种光致抗蚀剂。 抗反射层，第二介电层和第一介电层全部被蚀刻。 硬掩模层，抗反射层和第二介电层全部被蚀刻。 光致抗蚀剂层，硬掩模层和抗反射层全部被去除。 第一阻挡层顺应地形成在第二介电层和第一介电层的侧壁和暴露表面上以及在第一铜层的表面上。 种子层顺应地形成在阻挡层上。 通孔开口被填满，线路开口带有第二铜层。 最后，第二铜层可以被平坦化，直到暴露第二介电层。

公开(公告)号：US06387813B1

公开(公告)日：2002-05-14

申请号：US09721147

申请日：2000-11-22

申请人： Neng-Hui Yang ,  Ming-Sheng Yang ,  Chih-Chien Liu

发明人： Neng-Hui Yang ,  Ming-Sheng Yang ,  Chih-Chien Liu

IPC分类号： H01L21311

CPC分类号： H01L21/02063 ,  H01L21/31111

摘要： A method for stripping a low dielectric film with a high carbon content from silicon monitor chip. The silicon monitor chip is placed inside a plasma-enhanced chemical vapor deposition chamber and the surface is treated with oxygen plasma to form a silicon-rich oxide layer. A high-carbon-content low dielectric film is formed over the silicon-rich oxide for film quality inspection. After the film inspection, the silicon monitor chip is immersed in a solution containing ammonium hydroxide and hydrogen peroxide so that the surface of the high-carbon-content dielectric film is transformed from hydrophobic to hydrophilic. Hence, wetting capacity of subsequently applied hydrofluoric acid solution is enhanced. Finally, the silicon monitor chip is immersed in a hydrofluoric acid solution for stripping away the low dielectric film.

摘要翻译： 一种从硅监测芯片剥离高碳含量的低介电膜的方法。 将硅监测器芯片放置在等离子体增强化学气相沉积室的内部，并用氧等离子体处理该表面以形成富硅氧化物层。 在富含氧化硅的氧化物上形成高碳含量的低介电膜用于膜质量检验。 膜检查后，将硅监测器芯片浸入含有氢氧化铵和过氧化氢的溶液中，使得高碳含量的电介质膜的表面从疏水转变为亲水性。 因此，随后应用的氢氟酸溶液的润湿能力得到提高。 最后，将硅监测器芯片浸入氢氟酸溶液中以剥离低介电膜。

公开(公告)号：US06905938B2

公开(公告)日：2005-06-14

申请号：US10315128

申请日：2002-12-10

申请人： Ming-Sheng Yang ,  Chih-Chien Liu

发明人： Ming-Sheng Yang ,  Chih-Chien Liu

IPC分类号： H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/76

CPC分类号： H01L21/76801 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/318 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method includes providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etching mask. A second dielectric layer is formed between the conductor structures, which has a dielectric constant smaller than the first dielectric layer. The second dielectric layer also alternatively has air voids contained therein to reduce dielectric constant.

摘要翻译： 本发明提供一种形成低介电常数金属间介电层的方法。 该方法包括提供半导体衬底并在半导体衬底上形成第一电介质层。 在第一电介质层中形成导体结构。 通过使用导体结构作为蚀刻掩模来去除部分第一介电层。 在导体结构之间形成第二电介质层，导体结构的介电常数小于第一介电层。 第二电介质层也可选择地含有空气，以减少介电常数。

公开(公告)号：US06410106B1

公开(公告)日：2002-06-25

申请号：US09759570

申请日：2001-01-11

申请人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Ming-Sheng Yang

发明人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Ming-Sheng Yang

IPC分类号： H05H124

摘要： A method is used to form an intermetal dielectric layer. According to the invention, an unbiased-unclamped fluorinated silicate glass layer used as a protection layer is formed by high density plasma chemical vapor deposition on a biased-clamped fluorinated silicate glass layer formed by high density plasma chemical vapor deposition to prevent the biased-clamped fluorinated silicate glass layer from being exposed in a planarization process.

公开(公告)号：US06410446B1

公开(公告)日：2002-06-25

申请号：US09531974

申请日：2000-03-20

申请人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Ming-Sheng Yang

发明人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Ming-Sheng Yang

IPC分类号： H01L2131

CPC分类号： H01L21/02164 ,  C23C16/045 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/76801 ,  H01L21/76837

摘要： A method of filling a gap is proposed. The method of the invention is applied on a substrate which has conductive structures formed thereon. A HDPCVD is performed to form a dielectric layer on the substrate. The HDPCVD process comprises multi-steps. In a first step, a gas source is added to a deposition chamber to form dielectric material over the substrate. The gas source comprises reactive gas and inert gas. Thus, the first step can simultaneously perform deposition and sputtering. In a second step, the reactive gas is driven out of the deposition chamber. Only sputtering is used to remove a part of the dielectric material at top corners of the conductive structures. In a third step, the reactive gas is again added into the deposition chamber to deposit the dielectric material until filling the gap.

摘要翻译： 提出填补空白的方法。 本发明的方法应用于其上形成有导电结构的基板上。 执行HDPCVD以在衬底上形成电介质层。 HDPCVD过程包括多步骤。 在第一步骤中，将气体源添加到沉积室以在衬底上形成电介质材料。 气源包括反应性气体和惰性气体。 因此，第一步骤可以同时进行沉积和溅射。 在第二步骤中，反应气体被驱出离开沉积室。 仅使用溅射来去除导电结构的顶角处的介电材料的一部分。 在第三步骤中，将反应性气体再次添加到沉积室中以沉积介电材料直到填充间隙。

公开(公告)号：US06376394B1

公开(公告)日：2002-04-23

申请号：US09617458

申请日：2000-07-17

申请人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Ming-Sheng Yang

发明人： Cheng-Yuan Tsai ,  Chih-Chien Liu ,  Ming-Sheng Yang

IPC分类号： H01L2101

CPC分类号： H01L21/31053 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76834

摘要： A fabrication method for an inter-metal dielectric layer is applicable to multi-level interconnects. A substrate is provided with metal lines formed thereon. A first (fluorinated silicon glass) FSG layer with low fluorine content is then formed on the substrate, followed by forming a biased-clamped FSG layer on the first FSG layer. A second FSG layer with low fluorine content is formed on the biased-clamped layer, prior to forming an oxide cap layer on the second FSG layer. The oxide cap layer is planarized until the oxide cap layer is level with the second FSG layer.

摘要翻译： 金属间介电层的制造方法适用于多层互连。 衬底上形成有金属线。 然后在衬底上形成具有低氟含量的第一（氟化硅玻璃）FSG层，随后在第一FSG层上形成偏置夹持的FSG层。 在第二FSG层上形成氧化物覆盖层之前，在偏压夹层上形成具有低氟含量的第二FSG层。 氧化物盖层被平坦化，直到氧化物覆盖层与第二FSG层平齐。

公开(公告)号：US06323123B1

公开(公告)日：2001-11-27

申请号：US09655957

申请日：2000-09-06

申请人： Chih-Chien Liu ,  Cheng-Yuan Tsai ,  Anseime Chen ,  Ming-Sheng Yang

发明人： Chih-Chien Liu ,  Cheng-Yuan Tsai ,  Anseime Chen ,  Ming-Sheng Yang

IPC分类号： H01L214763

CPC分类号： H01L21/76808

摘要： A barrier layer is formed over the substrate by deposition, and a first dielectric is formed over the diffusion barrier layer by deposition. A etching stop layer and a second dielectric are formed in turn over the first dielectric by deposition. Next, a hard mask is formed on the second dielectric. Then, a photoresist layer is formed over the hard mask, and defining the photoresist layer. And then dry etching is carried out by means of the photoresist layer as the mask to form a via hole. A gap-filling material is filled on the second dielectric and into the via hole by conventional partial-cured (or un-cured) spin-on glass method. A anti-reflection layer is formed over the second dielectric by deposition. Another photoresist layer is formed on the anti-reflection coating and defined the photoresist layer, and to expose the partial surface of the via hole and the anti-reflection coating. Dry etching is proceed by means of the photoresist layer as a mask, and etching stop layer is as a etching terminal point to remove exposed partial surface of the bottom anti-reflection coating so as to form a trench. Then, the gap-filling material is removed by wet etching. Then a barrier layer is formed, and the seed layer is deposition on the barrier layer, and forming a conduct electricity metal layer on the seed layer. And then, the barrier layer and the anti-reflection coating are removed. Final, a barrier layer is deposition again.

摘要翻译： 通过沉积在衬底上形成阻挡层，并且通过沉积在扩散阻挡层上形成第一电介质。 通过沉积在第一电介质上依次形成蚀刻停止层和第二电介质。 接下来，在第二电介质上形成硬掩模。 然后，在硬掩模上形成光致抗蚀剂层，并且限定光致抗蚀剂层。 然后通过光致抗蚀剂层作为掩模进行干蚀刻以形成通孔。 间隙填充材料通过常规的部分固化（或未固化）旋涂玻璃方法填充在第二电介质上并进入通孔中。 通过沉积在第二电介质上形成抗反射层。 在防反射涂层上形成另一光致抗蚀剂层并限定光致抗蚀剂层，并露出通孔和防反射涂层的部分表面。 通过光致抗蚀剂层作为掩模进行干蚀刻，并且蚀刻停止层作为蚀刻终点以去除底部防反射涂层的暴露的部分表面以形成沟槽。 然后，通过湿蚀刻除去间隙填充材料。 然后形成阻挡层，种子层沉积在阻挡层上，并在籽晶层上形成导电电金属层。 然后，去除阻挡层和防反射涂层。 最后，阻挡层又是沉积。

公开(公告)号：US20140264913A1

公开(公告)日：2014-09-18

申请号：US13833464

申请日：2013-03-15

申请人： Chao-Yuan Huang ,  Yueh-Feng Ho ,  Ming-Sheng Yang ,  Hwi-Huang Chen

发明人： Chao-Yuan Huang ,  Yueh-Feng Ho ,  Ming-Sheng Yang ,  Hwi-Huang Chen

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprises a substrate, a through-silicon via (TSV) penetrating the substrate, at least one first interconnect structure traversing the TSV from the top and dividing a region right above the TSV into several sub-regions and being configured for interconnect routing of an active device and a plurality of second interconnect structures occupying the sub-regions right above the TSV and being configured for electrically coupling the TSV to a higher-level interconnect.

摘要翻译： 半导体器件包括衬底，穿透衬底的穿硅通孔（TSV），从顶部穿过TSV的至少一个第一互连结构，并将TSV正上方的区域划分成若干子区域并被配置用于互连路由 有源器件和多个第二互连结构占据TSV正上方的子区域并且被配置为将TSV电耦合到较高级互连。