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    Low-power USB flash card reader using bulk-pipe streaming with UAS command re-ordering and channel separation
    3.
    发明授权
    Low-power USB flash card reader using bulk-pipe streaming with UAS command re-ordering and channel separation 失效
    低功耗USB闪存卡阅读器，采用UAS命令重新排序和通道分离的大容量流式传输

    公开(公告)号：US08200862B2

    公开(公告)日：2012-06-12

    申请号：US12887477

    申请日：2010-09-21

    申请人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma

    发明人： Charles C. Lee ,  Frank Yu ,  Abraham C. Ma

    IPC分类号： G06F13/12 ,  G06F13/00 ,  G06F12/02

    CPC分类号： G06F13/28 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30 ,  Y02D10/14

    摘要： A flash-card reader improves transmission efficiency by using bulk streaming of multiple pipes. A bulk data-out pipe carries host write data to the card reader and can operate in parallel with a bulk data-in pipe that carries host read data that was read from a flash card attached to the card reader. Status packets do not block data packets since the he status packets are buffered through a separate status pipe, and commands are buffered through a command pipe. Flash data from multiple flash cards are interleaved as separate endpoints that share the bulk data-in pipe. A data in/out streaming state machine controls streaming bulk data through the bulk data-in and data-out pipes, while a status streaming state machine controls streaming status packets through the status pipe. Transaction overhead is reduced using bulk streaming where packets for several commands are combined into the same bulk streams.

    摘要翻译： 闪存卡读卡器通过使用多个管道的批量流传输来提高传输效率。 批量数据输出管道将主机写入数据传送到读卡器，并且可以与承载从附接到读卡器的闪存卡读取的主机读取数据的批量数据输入管并行操作。 状态数据包不会阻塞数据包，因为状态数据包通过单独的状态管道进行缓冲，命令通过命令管道缓冲。 来自多个闪存卡的闪存数据被交织为共享大容量数据管道的单独端点。 数据输入/输出流状态机通过批量数据输入和数据输出管道控制流批量数据，而状态流状态机通过状态管道控制流状态数据包。 使用批量流量减少事务开销，其中几个命令的数据包被组合成相同的批量流。

    Multi-operation write aggregator using a page buffer and a scratch flash block in each of multiple channels of a large array of flash memory to reduce block wear
    4.
    发明授权
    Multi-operation write aggregator using a page buffer and a scratch flash block in each of multiple channels of a large array of flash memory to reduce block wear 失效
    多操作写入聚合器使用大量闪存存储器的多个通道中的每个通道中的页面缓冲区和划痕闪存块来减少块磨损

    公开(公告)号：US08108590B2

    公开(公告)日：2012-01-31

    申请号：US12139842

    申请日：2008-06-16

    申请人： David Q. Chow ,  Frank Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

    发明人： David Q. Chow ,  Frank Yu ,  Charles C. Lee ,  Abraham C. Ma ,  Ming-Shiang Shen

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F21/32 ,  G06F21/78 ,  G06F2212/1036 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06K19/07 ,  G06K19/07354

    摘要： A flash system has multiple channels of flash memory chips that can be accessed in parallel. Host data is assigned to one of the channels by a multi-channel controller processor and accumulated in a multi-channel page buffer. When a page boundary in the page buffer is reached, the page buffer is written to a target physical block if full, or combined with old data fragments in an Aggregating Flash Block (AFB) when the logical-sector addresses (LSA's) match. Thus small fragments are aggregated using the AFB, reducing erases and wear of flash blocks. The page buffer is copied to the AFB when a STOP command occurs. Each channel has one or more AFB's, which are tracked by an AFB tracking table.

    摘要翻译： 闪存系统具有可以并行访问的多个闪存芯片的通道。 主机数据被多通道控制器处理器分配给一个通道，并且累积在多通道页缓冲器中。 当到达页面缓冲区中的页面边界时，如果逻辑扇区地址（LSA）匹配，则页缓冲区将被写入目标物理块（如果已满）或与聚合闪存块（AFB）中的旧数据片段组合。 因此，使用AFB聚集小片段，减少闪存块的擦除和磨损。 发生STOP命令时，页面缓冲区被复制到AFB。 每个通道都有一个或多个AFB，它们由AFB跟踪表进行跟踪。

    Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules
    5.
    发明申请
    Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules 有权
    命令排队智能存储传输管理器，用于将数据传送到原始NAND闪存模块

    公开(公告)号：US20110213921A1

    公开(公告)日：2011-09-01

    申请号：US13104257

    申请日：2011-05-10

    申请人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma

    发明人： Frank Yu ,  Charles C. Lee ,  Abraham C. Ma

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0607 ,  G06F2212/7208 ,  G11C13/0004

    摘要： A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.

    摘要翻译： 闪存模块具有通过NVM控制器通过物理块地址（PBA）总线访问的原始NAND闪存芯片。 NVM控制器位于闪存模块或固态硬盘（SSD）的系统板上。 NVM控制器将逻辑块地址（LBA）转换为物理块地址（PBA）。 闪存模块的多个通道之间的数据条带化和交织由智能存储事务管理器控制在高电平，而在信道内的进一步的交织和重新映射可由NVM控制器执行。 智能存储交换机使用SDRAM缓冲区，在写入闪存之前缓存主机数据。 Q-R指针表存储主机地址的商和余数。 剩余部分指向SDRAM中主机数据的位置。 命令队列存储主机命令的Q，R。

    Peripheral devices using phase-change memory
    6.
    发明授权
    Peripheral devices using phase-change memory 失效
    使用相变存储器的外围设备

    公开(公告)号：US07966429B2

    公开(公告)日：2011-06-21

    申请号：US11754332

    申请日：2007-05-28

    申请人： David Q. Chow ,  Charles C. Lee ,  Frank I-Kang Yu

    发明人： David Q. Chow ,  Charles C. Lee ,  Frank I-Kang Yu

    IPC分类号： G06F13/28 ,  G06F3/00 ,  G06F15/167 ,  G06F12/00 ,  G06F13/00

    CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C2213/79

    摘要： Peripheral devices store data in non-volatile phase-change memory (PCM). PCM cells have alloy resistors with high-resistance amorphous states and low-resistance crystalline states. The peripheral device can be a Serial AT-Attachment (SATA) or integrated device electronics (IDE) PCM solid-state disk or a Multi-Media Card/Secure Digital (MMC/SD) card. A peripheral PCM controller accesses PCM mass storage devices containing PCM memory chips that form a mass-storage device that is block-addressable rather than randomly-addressable. SATA, IDE, or MMC/SD transactions from a host bus are read by a bus transceiver on the peripheral PCM controller. Various routines that execute on a CPU in the peripheral PCM controller are activated in response to commands in the host-bus transactions. A PCM controller in the peripheral controller transfers data from the bus transceiver to the PCM mass storage devices for storage.

    摘要翻译： 外围设备将数据存储在非易失性相变存储器（PCM）中。 PCM单元具有具有高电阻非晶态和低电阻晶体态的合金电阻。 外围设备可以是串行AT附件（SATA）或集成设备电子设备（IDE）PCM固态磁盘或多媒体卡/安全数字（MMC / SD）卡。 外围PCM控制器访问包含PCM存储器芯片的PCM大容量存储设备，其形成可寻址的大容量存储设备，而不是可随机寻址的。 来自主机总线的SATA，IDE或MMC / SD事务由外围PCM控制器上的总线收发器读取。 响应于主机总线事务中的命令，激活在外围PCM控制器中的CPU上执行的各种例程。 外围控制器中的PCM控制器将数据从总线收发器传送到PCM大容量存储设备进行存储。

    High endurance non-volatile memory devices
    7.
    发明授权
    High endurance non-volatile memory devices 有权
    高耐久性非易失性存储器件

    公开(公告)号：US07953931B2

    公开(公告)日：2011-05-31

    申请号：US12035398

    申请日：2008-02-21

    申请人： I-Kang Yu ,  David Q. Chow ,  Charles C. Lee ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

    发明人： I-Kang Yu ,  David Q. Chow ,  Charles C. Lee ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

    IPC分类号： G06F12/12

    CPC分类号： G06F13/161 ,  G06F12/0246 ,  G06F12/0862 ,  G06F12/123 ,  G06F2212/7203 ,  G11C11/5621 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2211/5641 ,  G11C2211/5643

    摘要： High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

    摘要翻译： 描述了高耐久性非易失性存储器件（NVMD）。 高耐久性NVMD包括I / O接口，NVM控制器，CPU以及易失性存储器子系统和至少一个非易失性存储器（NVM）模块。 易失性存储器缓存子系统被配置为数据高速缓存子系统。 当NVMD适用于主机系统时，至少一个NVM模块被配置为数据存储器。 I / O接口被配置为从主机接收数据缓存子系统的传入数据，并将请求数据从数据缓存子系统发送到主机。 至少一个NVM模块可以包括至少第一和第二类型的NVM。 第一种类型包括SLC闪存，而第二种类型的MLC闪存。 NVM的第一种类型被配置为数据高速缓存子系统和第二类NVM之间的缓冲区。

    MEMORY ADDRESS MANAGEMENT SYSTEMS IN A LARGE CAPACITY MULTI-LEVEL CELL (MLC) BASED FLASH MEMORY DEVICE
    8.
    发明申请
    MEMORY ADDRESS MANAGEMENT SYSTEMS IN A LARGE CAPACITY MULTI-LEVEL CELL (MLC) BASED FLASH MEMORY DEVICE 有权
    基于大容量多级电池（MLC）的闪存存储器件中的存储器地址管理系统

    公开(公告)号：US20110093653A1

    公开(公告)日：2011-04-21

    申请号：US12980591

    申请日：2010-12-29

    申请人： Charles C. Lee ,  I-Kang Yu ,  David Nguyen ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

    发明人： Charles C. Lee ,  I-Kang Yu ,  David Nguyen ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

    IPC分类号： G06F12/00

    CPC分类号： H05K1/182 ,  G06F12/00 ,  H01R13/447 ,  H05K1/181 ,  H05K5/0278 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2203/1572

    摘要： Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

    摘要翻译： 描述了在大容量多级基于单元的闪存设备中管理存储器地址的方法和系统。 根据一个方面，一种闪存设备包括一个使用索引方案来管理逻辑到物理地址相关的处理单元。 闪存被分为N组。 每个集合包括多个条目（即，块）。 对于物理块号和相关联的页面使用信息（以下称为“PLTPPUI”）的N组部分逻辑条目号被存储在基于MLC的闪速存储器的保留区域中。 只有一个N集被加载以寻址相关和页面使用存储器（ACPUM），这是一个有限大小的随机存取存储器（RAM）。 在一个实施例中，静态RAM（SRAM）被实现用于地址相关的快速访问时间。 与数据传输请求一起接收的LSA指示将N组PLTPPUI中的哪一个加载到ACPUM中。

    Electronic data flash card with Reed Solomon error detection and correction capability
    9.
    发明授权
    Electronic data flash card with Reed Solomon error detection and correction capability 失效
    电子数据闪存卡，具有Reed Solomon错误检测和校正功能

    公开(公告)号：US07890846B2

    公开(公告)日：2011-02-15

    申请号：US11739613

    申请日：2007-04-24

    申请人： Charles C. Lee ,  I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

    发明人： Charles C. Lee ,  I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

    IPC分类号： H03M13/00

    CPC分类号： H03M13/1545 ,  G06F11/1068 ,  G06F11/1076 ,  H03M13/153 ,  H03M13/1535 ,  H03M13/6561

    摘要： One embodiment of the present includes a electronic data storage card having a Reed Solomon (RS) decoder having a syndrome calculator block responsive to a page of information, the page being organized into a plurality of data sections and the overhead being organized into a plurality of overhead sections. The syndrome calculator generates a syndrome for each of the data sections. The decoder further includes a root finder block responsive to the calculated syndrome and for generating at least two roots, a polynomial calculator block responsive to the at least two roots and operative to generate at least one error address, identifying a location in the data wherein the error lies, and an error symbol values calculator block coupled to the root finder and the polynomial calculator block and for generating a second error address, identifying a second location in the data wherein the error(s) lie.

    摘要翻译： 本发明的一个实施例包括具有Reed Solomon（RS）解码器的电子数据存储卡，该解码器具有响应于信息页的校正子计算器块，该页被组织成多个数据段，并且开销被组织成多个 架空部分。 综合征计算器为每个数据部分产生综合征。 解码器还包括响应于所计算的校正子并用于生成至少两个根的根取景器块，响应于至少两个根并且可操作地生成至少一个错误地址的多项式计算器块，识别数据中的位置，其中， 并且错误符号值计算器块耦合到根查找器和多项式计算器块，并用于产生第二错误地址，识别错误所在的数据中的第二位置。