公开(公告)号：US20150287667A1

公开(公告)日：2015-10-08

申请号：US14490683

申请日：2014-09-19

申请人： ChipMOS Technologies Inc.

发明人： Yu-Tang Pan ,  Shih-Wen Chou

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L21/48

CPC分类号： H01L23/49568 ,  H01L21/4828 ,  H01L21/4871 ,  H01L21/4875 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3736 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49586 ,  H01L23/49861 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/04042 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A chip package structure includes a lead frame having first and second patterned metal layers and an insulation layer, a chip, and an encapsulant covering the first patterned metal layer and the chip. The first patterned metal layer includes a chip pad with first recesses and bonding pads in the first recesses. A first groove exists between each bonding pad and the chip pad. The second patterned metal layer connecting the first patterned metal layer includes terminal pads and a heat dissipation block thermally coupled to the chip pad. The heat dissipation block includes second recesses where the terminal pads are located and electrically connected to the corresponding bonding pads. A second groove exists between each terminal pad and the heat dissipation block. The insulation layer is located between the bonding pads and the terminal pads. The chip on the chip pad is electrically connected to the bonding pads.

摘要翻译： 芯片封装结构包括具有第一和第二图案化金属层的引线框架和绝缘层，芯片以及覆盖第一图案化金属层和芯片的密封剂。 第一图案化金属层包括在第一凹部中具有第一凹部和接合焊盘的芯片焊盘。 在每个焊盘和芯片焊盘之间存在第一凹槽。 连接第一图案化金属层的第二图案化金属层包括端子焊盘和热耦合到芯片焊盘的散热块。 散热块包括第二凹部，其中端子焊盘位于并电连接到相应的焊盘。 在每个端子焊盘和散热块之间存在第二凹槽。 绝缘层位于接合焊盘和端子焊盘之间。 芯片焊盘上的芯片电连接到焊盘。

公开(公告)号：US09735092B2

公开(公告)日：2017-08-15

申请号：US15186558

申请日：2016-06-20

申请人： ChipMOS Technologies Inc.

发明人： Yu-Tang Pan ,  Shih-Wen Chou

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L23/373 ,  H01L23/00

CPC分类号： H01L23/49568 ,  H01L21/4828 ,  H01L21/4871 ,  H01L21/4875 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3736 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49586 ,  H01L23/49861 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/04042 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A manufacturing method of a chip package structure includes following steps. A substrate including a first metal layer, a second metal layer, and an insulation layer located between the first and the second metal layers is provided. A first groove is formed in the first metal layer to form a chip pad and bonding pads. The bonding pads are respectively located in recesses of the chip pad. A second groove is formed in the second metal layer to form a heat-dissipation block and terminal pads. The terminal pads are respectively located in recesses of the heat-dissipation block. Conductive vias are formed to connect the corresponding terminal pads and electrically connect the bonding pads with the terminal pads. A chip is disposed on the chip pad and electrically connected to the bonding pads. An encapsulant covering the chip is formed.

公开(公告)号：US20130140686A1

公开(公告)日：2013-06-06

申请号：US13647406

申请日：2012-10-09

申请人： ChipMOS Technologies Inc.

发明人： Yu-Tang Pan ,  Shih-Wen Chou

IPC分类号： H01L21/56 ,  H01L23/495

CPC分类号： H01L23/4334 ,  H01L21/4828 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/0612 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3862 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing a semiconductor package structure is provided. A heat-conductive block is adhered to a portion of a second surface of a conductive substrate via a first adhesive layer. An opening is formed by performing a half-etching process on a first surface of the conductive substrate. The remaining conductive substrate is patterned to form leads and expose a portion of the heat-conductive block. Each lead has a first portion and a second portion. A thickness of the first portion is greater than a thickness of the second portion. A first lower surface of the first portion and a second lower surface of the second portion are coplanar. A chip is disposed on the exposed portion of the heat-conductive block and electrically connected to the second portions of the leads. A first bottom surface of the heat-conductive block and a second bottom surface of a molding compound are coplanar.

摘要翻译： 提供一种制造半导体封装结构的方法。 导热块通过第一粘合剂层粘附到导电基底的第二表面的一部分。 通过在导电基板的第一表面上进行半蚀刻工艺来形成开口。 将剩余的导电衬底图案化以形成引线并暴露导热块的一部分。 每个引线具有第一部分和第二部分。 第一部分的厚度大于第二部分的厚度。 第一部分的第一下表面和第二部分的第二下表面是共面的。 芯片设置在导热块的暴露部分上并电连接到引线的第二部分。 导热块的第一底表面和模塑料的第二底表面是共面的。

公开(公告)号：US20150076670A1

公开(公告)日：2015-03-19

申请号：US14255973

申请日：2014-04-18

申请人： ChipMOS Technologies Inc.

发明人： Yu-Tang Pan ,  Shih-Wen Chou

IPC分类号： H01L23/31 ,  H01L23/373 ,  H01L21/56 ,  H01L23/00 ,  H01L23/552 ,  H01L23/433

CPC分类号： H01L23/552 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3737 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

摘要： A chip package structure and a manufacturing method thereof are provided. The chip package structure includes a substrate, a chip, a plurality of wires, a film layer, a carrier, and an encapsulant. The substrate has an upper surface and a lower surface. The chip is mounted on the upper surface of the substrate. The wires are electrically connected to the chip and the substrate respectively. The film layer is attached to the substrate and entirely encapsulates the chip and the wires. The carrier is adhered on the film layer. The encapsulant is disposed on the upper surface of the substrate, wherein the encapsulant has an electro-magnetic shielding filler. The encapsulant at least partially encapsulates the carrier and the film layer, and the encapsulant covers the chip and the wires.

摘要翻译： 提供了芯片封装结构及其制造方法。 芯片封装结构包括基板，芯片，多根导线，薄膜层，载体和密封剂。 基板具有上表面和下表面。 芯片安装在基板的上表面上。 电线分别与芯片和基板电连接。 膜层附着在基片上，完全封装芯片和电线。 载体粘附在膜层上。 密封剂设置在基板的上表面上，其中密封剂具有电磁屏蔽填料。 密封剂至少部分地封装载体和膜层，并且密封剂覆盖芯片和电线。

公开(公告)号：US20160293529A1

公开(公告)日：2016-10-06

申请号：US15186558

申请日：2016-06-20

申请人： ChipMOS Technologies Inc.

发明人： Yu-Tang Pan ,  Shih-Wen Chou

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/373 ,  H01L23/00

CPC分类号： H01L23/49568 ,  H01L21/4828 ,  H01L21/4871 ,  H01L21/4875 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3736 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49586 ,  H01L23/49861 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/04042 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A manufacturing method of a chip package structure includes following steps. A substrate including a first metal layer, a second metal layer, and an insulation layer located between the first and the second metal layers is provided. A first groove is formed in the first metal layer to form a chip pad and bonding pads. The bonding pads are respectively located in recesses of the chip pad. A second groove is formed in the second metal layer to form a heat-dissipation block and terminal pads. The terminal pads are respectively located in recesses of the heat-dissipation block. Conductive vias are formed to connect the corresponding terminal pads and electrically connect the bonding pads with the terminal pads. A chip is disposed on the chip pad and electrically connected to the bonding pads. An encapsulant covering the chip is formed.

摘要翻译： 芯片封装结构的制造方法包括以下步骤。 提供了包括第一金属层，第二金属层和位于第一和第二金属层之间的绝缘层的基板。 在第一金属层中形成第一凹槽以形成芯片焊盘和焊盘。 接合焊盘分别位于芯片焊盘的凹槽中。 在第二金属层中形成第二凹槽以形成散热块和端子垫。 端子焊盘分别位于散热块的凹槽中。 形成导电孔以连接相应的端子焊盘并将焊盘与端子焊盘电连接。 芯片设置在芯片焊盘上并电连接到焊盘。 形成覆盖芯片的密封剂。

公开(公告)号：US09437529B2

公开(公告)日：2016-09-06

申请号：US14490683

申请日：2014-09-19

申请人： ChipMOS Technologies Inc.

发明人： Yu-Tang Pan ,  Shih-Wen Chou

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L23/49568 ,  H01L21/4828 ,  H01L21/4871 ,  H01L21/4875 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3736 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49586 ,  H01L23/49861 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/04042 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A chip package structure includes a lead frame having first and second patterned metal layers and an insulation layer, a chip, and an encapsulant covering the first patterned metal layer and the chip. The first patterned metal layer includes a chip pad with first recesses and bonding pads in the first recesses. A first groove exists between each bonding pad and the chip pad. The second patterned metal layer connecting the first patterned metal layer includes terminal pads and a heat dissipation block thermally coupled to the chip pad. The heat dissipation block includes second recesses where the terminal pads are located and electrically connected to the corresponding bonding pads. A second groove exists between each terminal pad and the heat dissipation block. The insulation layer is located between the bonding pads and the terminal pads. The chip on the chip pad is electrically connected to the bonding pads.

摘要翻译： 芯片封装结构包括具有第一和第二图案化金属层的引线框架和绝缘层，芯片以及覆盖第一图案化金属层和芯片的密封剂。 第一图案化金属层包括在第一凹部中具有第一凹部和接合焊盘的芯片焊盘。 在每个焊盘和芯片焊盘之间存在第一凹槽。 连接第一图案化金属层的第二图案化金属层包括端子焊盘和热耦合到芯片焊盘的散热块。 散热块包括第二凹部，其中端子焊盘位于并电连接到相应的焊盘。 在每个端子焊盘和散热块之间存在第二凹槽。 绝缘层位于接合焊盘和端子焊盘之间。 芯片焊盘上的芯片电连接到焊盘。

公开(公告)号：US08691630B2

公开(公告)日：2014-04-08

申请号：US13647406

申请日：2012-10-09

申请人： ChipMOS Technologies Inc.

发明人： Yu-Tang Pan ,  Shih-Wen Chou

IPC分类号： H01L21/00

CPC分类号： H01L23/4334 ,  H01L21/4828 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/06 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/0612 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3862 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing a semiconductor package structure is provided. A heat-conductive block is adhered to a portion of a second surface of a conductive substrate via a first adhesive layer. An opening is formed by performing a half-etching process on a first surface of the conductive substrate. The remaining conductive substrate is patterned to form leads and expose a portion of the heat-conductive block. Each lead has a first portion and a second portion. A thickness of the first portion is greater than a thickness of the second portion. A first lower surface of the first portion and a second lower surface of the second portion are coplanar. A chip is disposed on the exposed portion of the heat-conductive block and electrically connected to the second portions of the leads. A first bottom surface of the heat-conductive block and a second bottom surface of a molding compound are coplanar.

摘要翻译： 提供一种制造半导体封装结构的方法。 导热块通过第一粘合剂层粘附到导电基底的第二表面的一部分。 通过在导电基板的第一表面上进行半蚀刻工艺来形成开口。 将剩余的导电衬底图案化以形成引线并暴露导热块的一部分。 每个引线具有第一部分和第二部分。 第一部分的厚度大于第二部分的厚度。 第一部分的第一下表面和第二部分的第二下表面是共面的。 芯片设置在导热块的暴露部分上并电连接到引线的第二部分。 导热块的第一底表面和模塑料的第二底表面是共面的。