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32 条记录 (耗时 0.023 秒)

    Process for producing multi-level metallization in an integrated circuit
    4.
    发明授权
    Process for producing multi-level metallization in an integrated circuit 失效
    在集成电路中生产多级金属化的工艺

    公开(公告)号：US5956618A

    公开(公告)日：1999-09-21

    申请号：US828155

    申请日：1997-03-27

    申请人： Chun-Ting Liu ,  Kuo-Hua Lee ,  Ruichen Liu

    发明人： Chun-Ting Liu ,  Kuo-Hua Lee ,  Ruichen Liu

    IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/027 ,  H01L21/304

    CPC分类号： H01L21/76838 ,  Y10S438/942

    摘要： A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.

    摘要翻译： 公开了一种用于制造多电平集成电路的方法，其利用网格图案，从其中选择性地去除与金属层相对应的部分以形成掩模，其随后用于在金属线之间的开放区域中沉积虚拟特征，从而 允许在金属层和虚拟特征上沉积基本上平面的电介质表面。

    Inter-wiring-layer capacitors
    6.
    发明授权
    Inter-wiring-layer capacitors 有权
    布线层电容器

    公开(公告)号：US06794694B2

    公开(公告)日：2004-09-21

    申请号：US09742314

    申请日：2000-12-21

    申请人： Philip W Diodato ,  Chun-Ting Liu ,  Ruichen Liu

    发明人： Philip W Diodato ,  Chun-Ting Liu ,  Ruichen Liu

    IPC分类号： H01L2976

    CPC分类号： H01L27/10852 ,  H01L21/76838 ,  H01L23/5223 ,  H01L27/10894 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit includes a semiconductor substrate with semiconductor devices formed therein and thereon, a first wiring layer located over the substrate, a second wiring layer located on the first wiring layer, and a capacitor. The capacitor has metal-based charge-storage electrodes that extend through the second wiring layer and at least part of the first wiring layer. The wiring layers have interconnect wire embedded therein.

    摘要翻译： 集成电路包括其上形成有半导体器件的半导体衬底及其上，位于衬底上的第一布线层，位于第一布线层上的第二布线层和电容器。 电容器具有延伸穿过第二布线层和至少部分第一布线层的金属基电荷存储电极。 布线层具有嵌入其中的互连线。

    Horizontal chalcogenide element defined by a pad for use in solid-state memories
    7.
    发明授权
    Horizontal chalcogenide element defined by a pad for use in solid-state memories 有权
    由用于固态存储器的焊盘限定的水平硫族化物元件

    公开(公告)号：US07683360B2

    公开(公告)日：2010-03-23

    申请号：US11378904

    申请日：2006-03-17

    申请人： Yi-Chou Chen ,  Hsiang-Lan Lung ,  Ruichen Liu

    发明人： Yi-Chou Chen ,  Hsiang-Lan Lung ,  Ruichen Liu

    IPC分类号： H01L29/04

    CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2463 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/1691

    摘要： A memory cell structure includes a substrate having a bottom electrode at least partially disposed within the substrate; a pad disposed at least partially over the substrate; a phase change element having a chalcogenide material, disposed at least partially over the substrate and adjacent to the pad, the phase change element being adjacent and operatively coupled to the bottom electrode; and a top electrode operatively coupled to the phase change element. Moreover, the pad is formed by a method including depositing a first material layer over the substrate, etching the first material layer to form a pad strip and to expose the bottom electrode, and etching the pad strip to from the pad.

    摘要翻译： 存储单元结构包括具有至少部分地设置在基板内的底电极的基板; 至少部分地设置在所述基板上的垫; 具有硫族化物材料的相变元件，至少部分地设置在所述衬底上并且与所述焊盘相邻，所述相变元件邻近并且可操作地耦合到所述底部电极; 以及可操作地耦合到相变元件的顶部电极。 此外，衬垫通过包括在衬底上沉积第一材料层的方法形成，蚀刻第一材料层以形成焊盘条并暴露底部电极，以及将焊盘条从焊盘蚀刻。

    Article comprising fluorinated amorphous carbon and process for fabricating article
    8.
    发明授权
    Article comprising fluorinated amorphous carbon and process for fabricating article 失效
    包含氟化无定形碳的制品及其制造方法

    公开(公告)号：US06147407A

    公开(公告)日：2000-11-14

    申请号：US49256

    申请日：1998-03-27

    申请人： Sungho Jin ,  Ruichen Liu ,  Chien-Shing Pai ,  Wei Zhu

    发明人： Sungho Jin ,  Ruichen Liu ,  Chien-Shing Pai ,  Wei Zhu

    IPC分类号： C23C14/06 ,  C23C14/22 ,  C23C14/34 ,  H01L21/312 ,  H01L23/532 ,  H01L23/48

    CPC分类号： C23C14/225 ,  C23C14/0605 ,  C23C14/3464 ,  H01L21/3127 ,  H01L23/5329 ,  H01L2924/0002

    摘要： The invention provides a device containing a low .kappa., hydrogen-free a-C:F layer with good adhesion and thermal stability. It was found that the combination of desirable properties was attainable by a relatively easy process, as compared to processes that utilize gaseous sources, such as CVD. Specifically, the a-C:F layer is formed by sputter deposition, using only solid sources for the fluorine and carbon, and in the absence of any intentionally-added hydrogen-containing source. The sputtering is performed such that the layer contains 20 to 60 at. % fluorine, and also, advantageously, such that the a-C:F exhibits a bandgap of about 2.0 eV or greater. The a-C:F layer formed by the process of the invention exhibits a dielectric constant, at 1 MHz and room temperature, of 3.0 or less, advantageously 2.5 or less, and more advantageously 2.1 or less, along with being thermally stable up to at least 350.degree. C., advantageously 450.degree. C., and exhibiting a stress of about 100 MPa or less, in absolute value.

    摘要翻译： 本发明提供含有低κ，无氢a-C：F层的装置，其具有良好的粘附性和热稳定性。 已经发现，与使用气体源（例如CVD）的方法相比，期望性质的组合可通过相对容易的方法获得。 具体地，通过溅射沉积形成a-C：F层，仅使用固体源作为氟和碳，并且在没有任何有意添加的含氢源的情况下。 进行溅射使得该层含有20至60at。 ％氟，并且还有利地使得a-C：F表现出约2.0eV或更大的带隙。 通过本发明的方法形成的aC：F层在1MHz和室温下表现出3.0或更小，有利地为2.5或更小，更优选为2.1或更小的介电常数，并且至少热稳定 350℃，有利地450℃，绝对值为约100MPa以下。

    Devices having shallow junctions
    9.
    发明授权
    Devices having shallow junctions 失效
    器件具有浅结

    公开(公告)号：US5063422A

    公开(公告)日：1991-11-05

    申请号：US515550

    申请日：1990-04-26

    申请人： Steven J. Hillenius ,  Joseph Lebowitz ,  Ruichen Liu ,  William T. Lynch

    发明人： Steven J. Hillenius ,  Joseph Lebowitz ,  Ruichen Liu ,  William T. Lynch

    IPC分类号： H01L21/225 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/36

    CPC分类号： H01L29/0847 ,  H01L21/2257 ,  H01L21/823814 ,  H01L27/0921 ,  H01L29/36 ,  H01L27/0928

    摘要： In CMOS based integrated circuits, stricter design rules require source and drain junctions shallower than 2500 .ANG.. By using a specific device configuration, a shallow junction is obtainable while resistance to latch-up is improved and other electrical properties, e.g., low leakage current, are maintained. To achieve this result the p-channel device should have an activation energy of the junction reverse leakage current region less than 1.12 eV, with a junction dopant region shallower than 1200 .ANG. and a monotonically decreasing junction dopant profile.

    摘要翻译： 在基于CMOS的集成电路中，更严格的设计规则要求源和漏接点比2500 ANGSTROM浅。 通过使用特定的器件配置，可以获得浅结，同时提高了闩锁的阻力，并且保持了其他电特性，例如低漏电流。 为了实现这一结果，p沟道器件应该具有小于1.12eV的结反向泄漏电流区域的激活能，其中掺杂剂区域比1200安培浅和单调递减的掺杂剂分布。

    Method of forming a contact structure
    10.
    发明授权
    Method of forming a contact structure 有权
    形成接触结构的方法

    公开(公告)号：US07371604B2

    公开(公告)日：2008-05-13

    申请号：US11545988

    申请日：2006-10-10

    申请人： Ming Hsiu Lee ,  Ruichen Liu

    发明人： Ming Hsiu Lee ,  Ruichen Liu

    IPC分类号： H01L21/00

    CPC分类号： H01L27/2409 ,  H01L21/76885 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

    摘要： Contact structures having I shapes and L shapes, and methods of fabricating I-shaped and L-shaped contact structures, are employed in semiconductor devices and, in certain instances, phase-change nonvolatile memory devices. The I-shaped and L-shaped contact structures produced by these methods exhibit relatively small active areas. The methods that determine the contact structure dimensions employ conventional semiconductor deposit and etch processing steps that are capable of creating readily reproducible results.

    摘要翻译： 具有I形状和L形的接触结构以及制造I形和L形接触结构的方法被采用在半导体器件中，并且在某些情况下采用相变非易失性存储器件。 通过这些方法产生的I形和L形接触结构表现出相对较小的活性区域。 确定接触结构尺寸的方法采用能够创建易于重现的结果的常规半导体沉积和蚀刻处理步骤。