公开(公告)号：US20110248343A1

公开(公告)日：2011-10-13

申请号：US12755720

申请日：2010-04-07

申请人： Dechao Guo ,  Marwan Khater ,  Christian Lavoie ,  Qiqing Ouyang ,  Zhen Zhang

发明人： Dechao Guo ,  Marwan Khater ,  Christian Lavoie ,  Qiqing Ouyang ,  Zhen Zhang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/265 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66643 ,  H01L29/7839

摘要： A method for forming a Schottky field effect transistor (FET) includes forming a gate stack on a silicon substrate, the gate stack comprising a gate polysilicon on top of a gate metal layer; depositing a metal layer over the gate polysilicon and the silicon substrate; annealing the metal layer, the gate polysilicon, and the silicon substrate such that the metal layer fully consumes the gate polysilicon to form a gate silicide and reacts with portions of the silicon substrate to form source/drain silicide regions in the silicon substrate; and in the event a portion of the metal layer does not react with the gate polysilicon or the silicon substrate, removing the unreacted portion of the metal layer.

摘要翻译： 一种用于形成肖特基场效应晶体管（FET）的方法包括在硅衬底上形成栅极堆叠，所述栅叠层在栅极金属层的顶部包括栅极多晶硅; 在栅极多晶硅和硅衬底上沉积金属层; 使金属层，栅极多晶硅和硅衬底退火，使得金属层完全消耗栅极多晶硅以形成栅极硅化物，并与硅衬底的部分反应以在硅衬底中形成源极/漏极硅化物区域; 并且在金属层的一部分不与栅极多晶硅或硅衬底反应的情况下，去除金属层的未反应部分。

公开(公告)号：US20080078997A1

公开(公告)日：2008-04-03

申请号：US11866440

申请日：2007-10-03

申请人： Marwan Khater

发明人： Marwan Khater

IPC分类号： H01L29/04

CPC分类号： H01L29/7378 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242

摘要： Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-are lithographic patterning. An opening is aligned above the dielectric pad and etched through an isolation oxide layer to an extrinsic base layer. The opening is equal to or greater in size than the dielectric pad. Another smaller opening is etched through the extrinsic base layer to the dielectric pad. A multi-step etching process is used to selectively remove the extrinsic base layer from the surfaces of the dielectric pad and then to selectively remove the dielectric pad. An emitter is then formed in the resulting trench. The resulting transistor structure has a distance between the edge of the lower section of the emitter and the edge of the extrinsic base that is minimized, thereby, reducing resistance.

摘要翻译： 公开了制造具有自对准凸起外部基极的双极晶体管的方法的实施例。 在该方法中，在具有最小尺寸的基板上形成介质垫，该最小尺寸能够使用当前的光刻图案来生产。 开口在电介质垫的上方对准，并通过隔离氧化层蚀刻到外在的基层。 开口的尺寸等于或大于电介质垫。 通过外部基极层蚀刻另一个较小的开口到电介质垫。 使用多步蚀刻工艺来从介电垫的表面选择性地去除非本征基层，然后选择性地去除介电垫。 然后在所得沟槽中形成发射极。 所得到的晶体管结构在发射极的下部边缘与外部基极的边缘之间具有最小化的距离，从而降低电阻。

公开(公告)号：US20060289852A1

公开(公告)日：2006-12-28

申请号：US11511047

申请日：2006-08-28

申请人： Gregory Freeman ,  Marwan Khater ,  Rajendran Krishnasamy ,  Kathryn Schonenberg ,  Andreas Stricker

发明人： Gregory Freeman ,  Marwan Khater ,  Rajendran Krishnasamy ,  Kathryn Schonenberg ,  Andreas Stricker

IPC分类号： H01L31/00

CPC分类号： H01L29/66068 ,  H01L29/2003 ,  H01L29/66242

摘要： A structure and method where C is incorporated into the collector region of a heterojunction bipolar device by a method which does not include C ion implantation are provided. In the present invention, C is incorporated into the collector by epitaxy in a perimeter trench etched into the collector region to better control the carbon profile and location. The trench is formed by etching the collector region using the trench isolation regions and a patterned layer over the center part of the collector as masks. Then, Si:C is grown using selective epitaxy inside the trench to form a Si:C region with sharp and well-defined edges. The depth, width and C content can be optimized to control and tailor the collector implant diffusion and to reduce the perimeter component of parasitic CCB.

摘要翻译： 提供了通过不包括C离子注入的方法将C并入到异质结双极器件的集电极区域中的结构和方法。 在本发明中，通过在刻蚀到集电极区域的周边沟槽中外延生长将C引入集电体，以更好地控制碳分布和位置。 通过使用沟槽隔离区域将集电极区域和在集电体的中心部分上的图案化层作为掩模来形成沟槽。 然后，使用沟槽内部的选择性外延生长Si：C以形成具有清晰且明确界定的边缘的Si：C区域。 可以优化深度，宽度和C含量以控制和定制集电极注入扩散并减少寄生C CB的周边分量。

公开(公告)号：US20060255415A1

公开(公告)日：2006-11-16

申请号：US10908448

申请日：2005-05-12

申请人： Gregory Freeman ,  Anil Chinthakindi ,  David Greenberg ,  Basanth Jagannathan ,  Marwan Khater ,  John Pekarik ,  Xudong Wang

发明人： Gregory Freeman ,  Anil Chinthakindi ,  David Greenberg ,  Basanth Jagannathan ,  Marwan Khater ,  John Pekarik ,  Xudong Wang

IPC分类号： H01L29/76

CPC分类号： H01L21/26586 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7843

摘要： A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge. In another embodiment, the stress is applied at the first magnitude to the drain edge while the zero or lower magnitude stress is applied to the drain edge.

摘要翻译： 提供一种场效应晶体管，其包括其中设置有源极区，沟道区和漏极区的邻接单晶半导体区。 沟道区域具有与源极区域共同的边缘作为源极边缘，并且沟道区域还具有与作为漏极边缘的漏极区域共同的边缘。 栅极导体覆盖沟道区域。 场效应晶体管还包括将源极边缘和漏极边缘的另一个施加不大于第二幅度的应力的第一幅度的应力仅施加到源极边缘和漏极边缘中的一个的结构， 其中所述第二幅度具有从零到所述第一幅度的大约一半的值。 在特定实施例中，将应力以第一幅度施加到源极边缘，同时零或较小幅度应力施加到漏极边缘。 在另一个实施例中，将应力以第一幅度施加到漏极边缘，同时将零或较小的幅度应力施加到漏极边缘。

公开(公告)号：US20060081934A1

公开(公告)日：2006-04-20

申请号：US11289915

申请日：2005-11-30

申请人： Marwan Khater ,  James Dunn ,  David Harame ,  Alvin Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen Onge ,  Andreas Stricker

发明人： Marwan Khater ,  James Dunn ,  David Harame ,  Alvin Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen Onge ,  Andreas Stricker

IPC分类号： H01L23/62

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

摘要翻译： 公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。 制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。 然后通过在第一非本征基层上的光刻形成电介质着色焊盘。 接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。 使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。 通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

公开(公告)号：US20050184359A1

公开(公告)日：2005-08-25

申请号：US10708340

申请日：2004-02-25

申请人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory Freeman ,  David Greenberg ,  Marwan Khater ,  William Tonti

发明人： Hiroyuki Akatsu ,  Rama Divakaruni ,  Gregory Freeman ,  David Greenberg ,  Marwan Khater ,  William Tonti

IPC分类号： H01L21/331 ,  H01L27/082 ,  H01L29/08 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/7378

摘要： A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.

摘要翻译： 提供了一种双极晶体管，其包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有基本上较小的面积 下表面。 双极晶体管还包括覆盖集电极基座的上表面的本征基极，与本征基极导电连接的升高的外部基极和覆盖本征基极的发射极。 在特定实施例中，发射器与收集器基座自对准，具有与收集器基座的中心线对准的中心线。

公开(公告)号：US20070007625A1

公开(公告)日：2007-01-11

申请号：US11160706

申请日：2005-07-06

申请人： Marwan Khater

发明人： Marwan Khater

IPC分类号： H01L21/331 ,  H01L27/082

CPC分类号： H01L29/7378 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242

摘要： Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-are lithographic patterning. An opening is aligned above the dielectric pad and etched through an isolation oxide layer to an extrinsic base layer. The opening is equal to or greater in size than the dielectric pad. Another smaller opening is etched through the extrinsic base layer to the dielectric pad. A multi-step etching process is used to selectively remove the extrinsic base layer from the surfaces of the dielectric pad and then to selectively remove the dielectric pad. An emitter is then formed in the resulting trench. The resulting transistor structure has a distance between the edge of the lower section of the emitter and the edge of the extrinsic base that is minimized, thereby, reducing resistance.

摘要翻译： 公开了制造具有自对准凸起外部基极的双极晶体管的方法的实施例。 在该方法中，在具有最小尺寸的基板上形成介质垫，该最小尺寸能够使用当前的光刻图案来生产。 开口在电介质垫的上方对准，并通过隔离氧化层蚀刻到外在的基层。 开口的尺寸等于或大于电介质垫。 通过外部基极层蚀刻另一个较小的开口到电介质垫。 使用多步蚀刻工艺来从介电垫的表面选择性地去除非本征基层，然后选择性地去除介电垫。 然后在所得沟槽中形成发射极。 所得到的晶体管结构在发射极的下部边缘与外部基极的边缘之间具有最小化的距离，从而降低电阻。

公开(公告)号：US20060065951A1

公开(公告)日：2006-03-30

申请号：US10953751

申请日：2004-09-29

申请人： Marwan Khater

发明人： Marwan Khater

IPC分类号： H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

摘要： A bipolar transistor is provided which includes a collector region, an intrinsic base region overlying the collector region and an emitter region overlying the intrinsic base region. An extrinsic base overlies a portion of the intrinsic base region. An epitaxial spacer layer is disposed between the collector region and the intrinsic base region in locations not underlying the emitter region.

公开(公告)号：US20060043529A1

公开(公告)日：2006-03-02

申请号：US10931660

申请日：2004-09-01

申请人： Dureseti Chidambarrao ,  Gregory Freeman ,  Marwan Khater

发明人： Dureseti Chidambarrao ,  Gregory Freeman ,  Marwan Khater

IPC分类号： H01L27/082

CPC分类号： H01L29/66242 ,  H01L21/8249 ,  H01L29/242 ,  H01L29/7378

摘要： A method of increasing mobility of charge carriers in a bipolar device comprises the steps of: creating compressive strain in the device to increase mobility of holes in an intrinsic base of the device; and creating tensile strain in the device to increase mobility of electrons in the intrinsic base of the device. The compressive and tensile strains are created by forming a stress layer in close proximity to the intrinsic base of the device. The stress layer is at least partially embedded in a base layer of the device, adjacent an emitter structure of the device. The stress layer has different lattice constant than the intrinsic base. Method and apparatus are described.

公开(公告)号：US20060017066A1

公开(公告)日：2006-01-26

申请号：US11231385

申请日：2005-09-21

申请人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

发明人： Peter Geiss ,  Marwan Khater ,  Qizhi Liu ,  Randy Mann ,  Robert Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas Stricker

IPC分类号： H01L31/109

CPC分类号： H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

摘要翻译： 提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。 在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。 本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。 凸起的外基极上面的硅化物以自对准的方式延伸到发射极。 发射极通过间隔物与硅化物分离。