公开(公告)号：US20110241115A1

公开(公告)日：2011-10-06

申请号：US12754079

申请日：2010-04-05

申请人： Christian Lavoie ,  Siegfried L. Maurer ,  Qiqing Ouyang ,  Paul Solomon ,  Zhen Zhang

发明人： Christian Lavoie ,  Siegfried L. Maurer ,  Qiqing Ouyang ,  Paul Solomon ,  Zhen Zhang

IPC分类号： H01L27/12 ,  H01L21/762 ,  H01L21/28

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/47 ,  H01L29/4908 ,  H01L29/66772 ,  H01L29/7839 ,  H01L29/78654

摘要： A Schottky field effect transistor (FET) includes a gate stack located on a silicon on insulator (SOI) layer, the gate stack comprising a gate silicide region; and source/drain silicide regions located in the SOI layer, the source/drain silicide regions comprising and at least one of sulfur and fluorine, wherein an interface comprising arsenic is located between each of the source/drain silicide regions and the SOI layer. A method of forming a contact, the contact comprising a silicide region adjacent to a silicon region, includes co-implanting the silicide region with arsenic and at least one of sulfur and fluorine; and drive-in annealing the co-implanted silicide region to diffuse the arsenic to an interface between the silicide region and the silicon region.

摘要翻译： 肖特基场效应晶体管（FET）包括位于绝缘体上硅（SOI）层上的栅极堆叠，栅极叠层包括栅极硅化物区域; 位于SOI层中的源极/漏极硅化物区域，源极/漏极硅化物区域包括硫和氟中的至少一个，其中包含砷的界面位于每个源/漏硅化物区域和SOI层之间。 一种形成接触的方法，包括与硅区相邻的硅化物区的接触包括将砷化硅区域与砷和硫和氟中的至少一种共同注入; 并且将共注入的硅化物区域驱入退火以将砷扩散到硅化物区域和硅区域之间的界面。

公开(公告)号：US08664721B2

公开(公告)日：2014-03-04

申请号：US13569741

申请日：2012-08-08

申请人： Christian Lavoie ,  Tak H. Ning ,  Qiqing Ouyang ,  Paul Solomon ,  Zhen Zhang

发明人： Christian Lavoie ,  Tak H. Ning ,  Qiqing Ouyang ,  Paul Solomon ,  Zhen Zhang

IPC分类号： H01L27/12 ,  H01L29/45

CPC分类号： H01L29/66575 ,  H01L21/265 ,  H01L21/28097 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7839

摘要： A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer.

摘要翻译： 场效应晶体管（FET）包括位于硅层中的源极/漏极硅化物区域; 位于源/漏硅化物区域和硅层之间的源极/漏极界面层; 以及包括位于硅层上的栅极氧化物层，位于栅极氧化物层上的栅极界面层和位于栅极界面层上的栅极硅化物的完全硅化栅极堆叠。

公开(公告)号：US20120298965A1

公开(公告)日：2012-11-29

申请号：US13568839

申请日：2012-08-07

申请人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

发明人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

IPC分类号： H01L29/772 ,  B82Y99/00

CPC分类号： H01L29/0673 ,  H01L21/823814 ,  H01L29/41791

摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

摘要翻译： 一种多栅格结构，包括半导体衬底; 位于基板上的小于20纳米厚的超薄硅或碳体; 选择性地位于超薄硅或碳体的侧表面和顶表面上的无电沉积金属层，并且选择性地位于多结构结构的顶部上以与超薄硅或碳体电接触并最小化寄生电阻 并且其中位于其上的超薄硅或碳体和金属层形成源区和漏区以及制造该结构的工艺。

公开(公告)号：US20120132989A1

公开(公告)日：2012-05-31

申请号：US12955388

申请日：2010-11-29

申请人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

发明人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/0673 ,  H01L21/823814 ,  H01L29/41791

摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

公开(公告)号：US09099327B2

公开(公告)日：2015-08-04

申请号：US13568839

申请日：2012-08-07

申请人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

发明人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

IPC分类号： H01L29/06 ,  H01L21/8238 ,  H01L29/417

CPC分类号： H01L29/0673 ,  H01L21/823814 ,  H01L29/41791

摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

摘要翻译： 一种多栅格结构，包括半导体衬底; 位于基板上的小于20纳米厚的超薄硅或碳体; 选择性地位于超薄硅或碳体的侧表面和顶表面上的无电沉积金属层，并且选择性地位于多结构结构的顶部上以与超薄硅或碳体电接触并最小化寄生电阻 并且其中位于其上的超薄硅或碳体和金属层形成源区和漏区以及制造该结构的工艺。

公开(公告)号：US20110316565A1

公开(公告)日：2011-12-29

申请号：US12825527

申请日：2010-06-29

申请人： Dechao Guo ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Yanning Sun ,  Zhen Zhang

发明人： Dechao Guo ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Yanning Sun ,  Zhen Zhang

IPC分类号： G01R27/26 ,  H01L21/338 ,  H01L29/772 ,  H01L29/775

CPC分类号： G01N27/4145 ,  G01N27/4146 ,  H01L29/0673

摘要： A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.

摘要翻译： 肖特基结的硅纳米线场效应生物传感器/分子检测器，纳米线厚度为10纳米或更小，并具有对准的源极/漏极功能，以提高灵敏度。 纳米线通道涂覆有目标分子吸收的表面处理，其可以充分调节肖特基结之间的通道的电导率以定性和定量地测量分子的存在和量。

公开(公告)号：US20110248343A1

公开(公告)日：2011-10-13

申请号：US12755720

申请日：2010-04-07

申请人： Dechao Guo ,  Marwan Khater ,  Christian Lavoie ,  Qiqing Ouyang ,  Zhen Zhang

发明人： Dechao Guo ,  Marwan Khater ,  Christian Lavoie ,  Qiqing Ouyang ,  Zhen Zhang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/265 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66643 ,  H01L29/7839

摘要： A method for forming a Schottky field effect transistor (FET) includes forming a gate stack on a silicon substrate, the gate stack comprising a gate polysilicon on top of a gate metal layer; depositing a metal layer over the gate polysilicon and the silicon substrate; annealing the metal layer, the gate polysilicon, and the silicon substrate such that the metal layer fully consumes the gate polysilicon to form a gate silicide and reacts with portions of the silicon substrate to form source/drain silicide regions in the silicon substrate; and in the event a portion of the metal layer does not react with the gate polysilicon or the silicon substrate, removing the unreacted portion of the metal layer.

摘要翻译： 一种用于形成肖特基场效应晶体管（FET）的方法包括在硅衬底上形成栅极堆叠，所述栅叠层在栅极金属层的顶部包括栅极多晶硅; 在栅极多晶硅和硅衬底上沉积金属层; 使金属层，栅极多晶硅和硅衬底退火，使得金属层完全消耗栅极多晶硅以形成栅极硅化物，并与硅衬底的部分反应以在硅衬底中形成源极/漏极硅化物区域; 并且在金属层的一部分不与栅极多晶硅或硅衬底反应的情况下，去除金属层的未反应部分。

公开(公告)号：US08936978B2

公开(公告)日：2015-01-20

申请号：US12955388

申请日：2010-11-29

申请人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

发明人： Wilfried Haensch ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Xiaoyan Shao ,  Paul M. Solomon ,  Zhen Zhang ,  Bin Yang

IPC分类号： H01L29/06 ,  H01L29/417

CPC分类号： H01L29/0673 ,  H01L21/823814 ,  H01L29/41791

摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

公开(公告)号：US20120299102A1

公开(公告)日：2012-11-29

申请号：US13569741

申请日：2012-08-08

申请人： Christian Lavoie ,  Tak H. Ning ,  Qiqing Ouyang ,  Paul Solomon ,  Zhang Zhen

发明人： Christian Lavoie ,  Tak H. Ning ,  Qiqing Ouyang ,  Paul Solomon ,  Zhang Zhen

IPC分类号： H01L29/786

CPC分类号： H01L29/66575 ,  H01L21/265 ,  H01L21/28097 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7839

摘要： A field effect transistor (FET) includes source/drain silicide regions located in a silicon layer; source/drain interfacial layers located in between the source/drain silicide regions and the silicon layer; and a fully silicided gate stack comprising a gate oxide layer located on the silicon layer, a gate interfacial layer located on the gate oxide layer, and a gate silicide located on the gate interfacial layer.

摘要翻译： 场效应晶体管（FET）包括位于硅层中的源极/漏极硅化物区域; 位于源/漏硅化物区域和硅层之间的源极/漏极界面层; 以及包括位于硅层上的栅极氧化物层，位于栅极氧化物层上的栅极界面层和位于栅极界面层上的栅极硅化物的完全硅化栅极堆叠。

公开(公告)号：US20110241116A1

公开(公告)日：2011-10-06

申请号：US12754881

申请日：2010-04-06

申请人： Christian Lavoie ,  Tak H. Ning ,  Qiqing Ouyang ,  Paul Solomon ,  Zhang Zhen

发明人： Christian Lavoie ,  Tak H. Ning ,  Qiqing Ouyang ,  Paul Solomon ,  Zhang Zhen

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66575 ,  H01L21/265 ,  H01L21/28097 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7839

摘要： A method for forming a field effect transistor (FET) includes forming a gate stack on a silicon layer, the gate stack comprising a gate polysilicon on top of a gate oxide layer; forming a fully silicided gate from the gate polysilicon and forming source/drain silicide regions in the silicon layer; implanting the gate silicide and the source/drain silicide with dopants; and performing rapid thermal annealing to form a gate interfacial layer in between the gate silicide and the gate oxide layer, and source/drain interfacial layers between the source/drain silicide regions and the silicon layer.

摘要翻译： 一种用于形成场效应晶体管（FET）的方法包括在硅层上形成栅叠层，所述栅叠层在栅极氧化层的顶部包括栅极多晶硅; 从栅极多晶硅形成完全硅化的栅极，并在硅层中形成源极/漏极硅化物区域; 用掺杂剂注入栅极硅化物和源极/漏极硅化物; 并且执行快速热退火以在栅极硅化物和栅极氧化物层之间形成栅极界面层，以及源极/漏极硅化物区域和硅层之间的源极/漏极界面层。