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公开(公告)号：US06246619B1
公开(公告)日：2001-06-12
申请号：US09498985
申请日：2000-02-07
申请人： Christopher Ematrudo , Jeffrey S. Earl , Michael C. Stephens, Jr. , Luigi Ternullo, Jr. , Michael F. Vincent
发明人： Christopher Ematrudo , Jeffrey S. Earl , Michael C. Stephens, Jr. , Luigi Ternullo, Jr. , Michael F. Vincent
IPC分类号： G11C2900
摘要： A circuit for a DRAM is described which, when in test mode, notifies a tester when the self-refresh operation of a dynamic random access memory (DRAM) reaches various stages of completion. By signaling the tester when, i.e., ⅛, ¼, ½, etc. of the self-refresh cycle is reached, the amount of time needed for verification of the self-refresh oscillator frequency is reduced correspondingly by a factor of 8, 4, 2 etc. The signaling of a partial test time is achieved by adding self-refresh status logic circuits which decode the high order most significant bits of the refresh address counter. The activation of the third most significant bit signals completion of ⅛th of the self-refresh cycle, the activation of the second most significant bit signals completion of ¼th of the self-refresh cycle, the activation of the most significant bit signals completion of ½ of the self-refresh cycle, and deactivation of the most significant bit signals completion of the self-refresh cycle.
摘要翻译： 描述了用于DRAM的电路，当处于测试模式时，当动态随机存取存储器（DRAM）的自刷新操作达到各种完成阶段时，通知测试者。 当达到自刷新周期的⅛，¼，½等时，通过信号通知测试仪，验证自刷新振荡器频率所需的时间相应减少了8倍，4倍， 2等等。通过添加对刷新地址计数器的高阶最高有效位进行解码的自刷新状态逻辑电路来实现部分测试时间的信令。 第三最高有效位的激活信号完成自刷新周期的第‧秒，第二最高有效位信号的激活完成自刷新周期的第1/4，最高有效位信号的激活完成为1/2的 自刷新周期，以及最高有效位信号的去激活完成自刷新周期。
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2.发明授权Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices 有权多个数据时钟激活与可编程延迟，用于多个CAS延迟存储器件
公开(公告)号：US6061296A
公开(公告)日：2000-05-09
申请号：US135252
申请日：1998-08-17
CPC分类号： G11C7/1039 , G11C7/1045 , G11C7/1051 , G11C7/1072
摘要： A timing scheme for multiple data clock activation with programmable delay for use in accessing a multiple CAS latency memory device. A multi-stage data propagation path is used to propagate a bit being accessed from a memory array of the device to an output line. Timing signals are generated so that in a CAS latency three mode, the timing signal that activates the next to last stage of the propagation path is triggered by an output clock signal that activates the last stage of the propagation path so that pulse from the output clock signal does not overlap with pulses of the timing signal that activates the previous stage. This timing scheme ensures the data lines feeding the last stage are not being restored while the last stage is sensing these data lines. A programmable delay circuit is used to adjust the timing of the output clock signal.
摘要翻译： 具有可编程延迟的多数据时钟激活的定时方案，用于访问多个CAS延迟存储器设备。 多级数据传播路径用于将正在访问的位从设备的存储器阵列传播到输出线。 产生定时信号，使得在CAS等待三个模式中，激活传播路径的最后一级的定时信号由激活传播路径的最后一级的输出时钟信号触发，使得来自输出时钟的脉冲 信号与激活前一级的定时信号的脉冲不重叠。 该定时方案确保在最后一级感测这些数据线时，馈送最后一级的数据线不被恢复。 可编程延迟电路用于调整输出时钟信号的时序。
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公开(公告)号：US6060873A
公开(公告)日：2000-05-09
申请号：US266006
申请日：1999-03-12
IPC分类号： G05F3/16
CPC分类号： G11C5/147
摘要： A regulator system for an on-chip-generated supply voltage includes a voltage detection circuit, a power-up mode detection circuit, a normal mode detection path, and a power-up detection path. The voltage detection circuit monitors the on-chip-generated supply voltage and generates a signal that indicates the level of this supply voltage. The power-up mode detection circuit detects when the chip is in the power-up mode and generates a path select signal. The path select signal causes the regulator system to select the power-up detection path during the power-up mode and to select the normal detection path when not in the power-up mode. The power-up detection path includes voltage regulation circuitry that does not rely on a reference voltage. In one embodiment, the power-up detection path includes a logic gate coupled to receive the signal from the voltage detector. The logic gate is skewed to have a trip point that corresponds to voltage level slightly greater than that of the external supply voltage. The logic gate controls the on-chip voltage generator to maintain the on-chip-generated voltage level at a magnitude greater than that of the external supply voltage. During power-up, the power-up detection circuit selects the power-up detection path, thereby avoiding the need to disable the on-chip voltage generator as in conventional systems that depend on a reference voltage.
摘要翻译： 用于片上生成的电源电压的调节器系统包括电压检测电路，上电模式检测电路，正常模式检测路径和上电检测路径。 电压检测电路监视片上产生的电源电压并产生指示该电源电压的电平的信号。 上电模式检测电路检测芯片何时处于上电模式并产生路径选择信号。 路径选择信号使调节器系统在上电模式下选择上电检测路径，并在不处于上电模式时选择正常检测路径。 上电检测路径包括不依赖于参考电压的电压调节电路。 在一个实施例中，上电检测路径包括耦合以接收来自电压检测器的信号的逻辑门。 逻辑门偏置为具有对应于略高于外部电源电压的电压电平的跳变点。 逻辑门控制片上电压发生器，以将片上生成的电压电平维持在大于外部电源电压的幅度。 在上电期间，上电检测电路选择上电检测路径，从而避免了像依赖于参考电压的常规系统中的片上电压发生器的禁用。
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公开(公告)号：US06208197B1
公开(公告)日：2001-03-27
申请号：US09262503
申请日：1999-03-04
IPC分类号： G05F110
CPC分类号： H02M3/07
摘要： A charge pump limits the voltages at nodes internal to the charge pump to reduce the risk of junction breakdown in the charge pump. The charge pump includes a first pump circuit, a second pump circuit, a first clamp and a second clamp. The first clamp limits the voltage level of a well by providing a current path from the well to the output lead when the voltage level of the well reaches a first predetermined limit. The voltage level at a node from which charge is redistributed to the well is limited by the second clamp, which is configured to provide a conductive path from the node to the output lead when the voltage level of the node reaches a second predetermined limit. The pump circuits can each include a logic circuit that is configured, depending on the level of an external supply voltage, to reduce the rate at which the capacitor node is boosted when the external supply voltage is relatively high. The logic circuit can also vary the voltage difference between the capacitor node and the external supply voltage to decrease the relative voltage level at the capacitor node relative to the level of the external supply voltage. These features also help reduce the risk of junction breakdown in the charge pump.
摘要翻译： 电荷泵限制电荷泵内部节点处的电压，以降低电荷泵中结点破裂的风险。 电荷泵包括第一泵电路，第二泵电路，第一夹具和第二夹具。 当阱的电压水平达到第一预定极限时，第一钳位器通过提供从井到输出引线的电流路径来限制阱的电压电平。 电荷再分配到阱的节点处的电压电平受到第二钳位限制，第二钳位器被配置为当节点的电压电平达到第二预定极限时，提供从节点到输出引线的导电路径。 泵电路可以各自包括根据外部电源电压的电平配置的逻辑电路，以在外部电源电压相对较高时降低电容器节点升压的速率。 逻辑电路还可以改变电容器节点和外部电源电压之间的电压差，以降低电容器节点处的相对电压相对于外部电源电压的电平。 这些功能还有助于降低电荷泵中结点破裂的风险。
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公开(公告)号：US06052328A
公开(公告)日：2000-04-18
申请号：US995379
申请日：1997-12-22
IPC分类号： G11C8/00 , G11C11/401
CPC分类号： G11C7/1048 , G11C11/4076 , G11C11/4091 , G11C11/4096 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/1093 , G11C7/1096 , G11C7/222
摘要： The present invention provides a method and apparatus that accomplishes a high performance, random read/write SDRAM design by synchronizing the read and write operations at the data line sense amplifier. This enables the design to perform random read and write operations without varying cycle time issues or unbalanced margin issues. The data lines are used as bi-directional lines to accomplish high performance reads and writes with minimal additional wiring overhead required. During a read operation, read data is transferred from the memory cells of the device across a series of consecutive pairs of data lines to an input/output port of the memory device. The first pair of data lines is coupled to a data line sense amplifier. The additional pairs of data lines are coupled to additional amplifiers. During a read operation, data is transferred across the consecutive pairs of data lines according to the timing cycles of the respective amplifiers. In order to quickly drive the data signals during a write operation up the series of consecutive pairs of data lines, the timing signals for each of the pairs of data lines except the first pair of data lines are disabled so that the data lines are allowed to float, and then the data lines are overdriven with the write data so that the write data quickly transitions up the series of data lines to the selected data line sense amplifier, where it arrives at approximately the same time that read data normally arrives during the timing cycle for the data line sense amplifier.
摘要翻译： 本发明提供一种通过使数据线读出放大器的读和写操作同步来实现高性能随机读/写SDRAM设计的方法和装置。 这使得设计能够执行随机读取和写入操作，而不会改变周期时间问题或不平衡边际问题。 数据线用作双向线路，以最少的附加线路开销实现高性能读写。 在读取操作期间，将读取数据从设备的存储器单元跨越一系列连续的数据线对传送到存储器件的输入/输出端口。 第一对数据线耦合到数据线读出放大器。 附加的数据线对耦合到附加的放大器。 在读取操作期间，根据相应放大器的定时周期，在连续的数据线对之间传送数据。 为了在写入操作期间快速驱动数据信号，连续的一连串数据线对，除了第一对数据线之外的每对数据线的定时信号被禁用，使得数据线被允许 浮动，然后数据线与写入数据过载，使得写入数据快速地将数据线系列快速转换到所选择的数据线读出放大器，其中它大约在读取数据在定时期间正常到达的时间到达 周期为数据线读出放大器。
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6.发明授权Semiconductor memory device with improved read signal generation of data lines and assisted precharge to mid-level 失效半导体存储器件具有改进的数据线读信号生成和辅助预充电到中级
公开(公告)号：US5796665A
公开(公告)日：1998-08-18
申请号：US958205
申请日：1997-10-17
CPC分类号： G11C7/1078 , G11C7/1006 , G11C7/1048 , G11C7/1051
摘要： A semiconductor memory device with a pair of data lines for reading and writing data signals to and from a matrix of memory cells and an accelerator circuit for accelerating the generation of a data signal on at least one of the data lines is disclosed. Slow signal generation on the data lines is due to the characteristics of NFET pass gates passing high signals, or PFET pass gates passing low signals. In an implementation using NFET pass gates, the accelerator circuit includes a pair of cross-coupled PFET transistors, one of which is activated by the low signal on the opposing data line. The drains of the cross-coupled PFET transistors are coupled to the data lines, such that when the low signal on the opposing data line activates one of the PFETs, it supplies additional current to the data line receiving the high signal, so as to accelerate the generation of the high signal on the data line. Faster signal generation allows for the data line latches of the circuit to be set earlier, thus allowing the read cycle of the memory device to be faster. An additional result of the increased signal generation on the data line that is receiving a high signal is that at the end of the cycle when the two data lines are coupled together, their average voltage due to charge sharing tends to be closer to a desired midlevel voltage such that less power is required to bring the two data lines to the desired mid-level voltage at the end of the signal cycle.
摘要翻译： 公开了一种半导体存储器件，其具有用于将数据信号读入和写入存储器单元矩阵的一对数据线，以及用于加速至少一条数据线上的数据信号的产生的加速器电路。 数据线上的慢信号产生是由于NFET通过栅极通过高信号的特性，或PFET通过门通过低信号。 在使用NFET通过门的实现中，加速器电路包括一对交叉耦合的PFET晶体管，其中之一由相对数据线上的低信号激活。 交叉耦合PFET晶体管的漏极耦合到数据线，使得当相对数据线上的低信号激活PFET之一时，它向接收高信号的数据线提供附加电流，以便加速 在数据线上产生高信号。 更快的信号产生允许更早地设置电路的数据线锁存器，从而允许存储器件的读取周期更快。 在接收高信号的数据线上增加的信号产生的附加结果是在两个数据线耦合在一起的周期结束时，由于电荷共享而导致的它们的平均电压倾向于更接近于期望的中间级 电压，使得在信号周期结束时需要更少的功率来使两条数据线达到期望的中间电平电压。
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公开(公告)号：US07102421B1
公开(公告)日：2006-09-05
申请号：US09064884
申请日：1998-04-20
IPC分类号： G05F1/10
CPC分类号： G11C5/147 , G01R31/30 , G01R31/31701 , G11C29/12 , G11C29/12005
摘要： A voltage regulation scheme for an on-chip voltage generator includes a voltage sensing circuit (VSC) and a configurable buffer circuit (CBC) to regulate the on-chip voltage generator. The CBC generates an output signal that is received by the on-chip voltage generator to activate and de-activate the voltage generator. The VSC generates a voltage level detection (VLD) signal having a voltage level that is a function of the level of the on-chip generated voltage. The CBC receives a control signal that is used to dynamically configure the chip into an operational mode, as well as the VLD signal. In response to the control signal, the switch threshold of the CBC is configured to a predetermined level corresponding to the selected operational mode. The predetermined trip point causes the CBC to appropriately activate and de-activate the on-chip voltage generator to regulate the on-chip generated voltage at the level required by the configured operational mode. One embodiment of the CBC uses a configurable pull-up circuit to alter its switch threshold or trip point. The configurable pull-up circuit is used to pull-up the voltage at an intermediate node that is buffered and propagated to the on-chip voltage generator to activate and de-activate the voltage generator. The configurable pull-up circuit more strongly pulls up this voltage in one operational mode compared to another operational mode to alter the switch threshold.
摘要翻译： 用于片上电压发生器的电压调节方案包括用于调节片上电压发生器的电压感测电路（VSC）和可配置缓冲电路（CBC）。 CBC产生由片上电压发生器接收的输出信号以激活和去激活电压发生器。 VSC产生电压电平检测（VLD）信号，其具有作为片上产生电压的电平的函数的电压电平。 CBC接收用于将芯片动态地配置为操作模式的控制信号以及VLD信号。 响应于控制信号，CBC的开关阈值被配置为与所选择的操作模式对应的预定电平。 预定的跳闸点使得CBC适当地激活和去激活片上电压发生器，以将片上产生的电压调节在所配置的操作模式所要求的水平。 CBC的一个实施例使用可配置的上拉电路来改变其开关阈值或跳变点。 可配置的上拉电路用于将缓冲并传播到片上电压发生器的中间节点处的电压上拉以激活和去激活电压发生器。 与其他操作模式相比，可配置上拉电路在一个操作模式下更强大地拉高电压，以改变开关阈值。
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公开(公告)号：US5973895A
公开(公告)日：1999-10-26
申请号：US56546
申请日：1998-04-07
摘要： A circuit for disabling a two-phase charge pump includes a pump select circuit and a disable control circuit. The pump select circuit is configured to select one control signal from a plurality of control signals in response to at least one select signal. The selected signal is in effect provided to the disable control circuit, which also receives a pump disable signal. A voltage sensing circuit asserts the pump disable signal when the pumped voltage reaches a predetermined maximum level. While the pump disable signal is de-asserted, the disable control circuit in effect provides the selected signal to the two-phase charge pump as a pump control signal. However, when the pump disable signal is asserted, the disable control signal latches the current logic level of the pump control signal so that the pump control signal does not transition while the pump disable signal is asserted. As a result, the two-phase charge pump is prevented from performing an extra pump cycle that would cause the pumped voltage to exceed the predetermined maximum level.
摘要翻译： 用于禁用两相电荷泵的电路包括泵选择电路和禁用控制电路。 泵选择电路被配置为响应于至少一个选择信号从多个控制信号中选择一个控制信号。 选择的信号实际上提供给禁用控制电路，其也接收泵禁止信号。 当泵浦电压达到预定的最大电平时，电压感测电路确定泵禁止信号。 当泵禁用信号被取消断言时，禁用控制电路实际上将选择的信号提供给两相电荷泵作为泵控制信号。 然而，当泵禁止信号被确认时，禁用控制信号锁存泵控制信号的当前逻辑电平，使得泵控制信号在泵禁能信号被断言时不转换。 结果，防止两相电荷泵执行额外的泵浦循环，这将使泵送的电压超过预定的最大电平。
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公开(公告)号：US6016072A
公开(公告)日：2000-01-18
申请号：US46408
申请日：1998-03-23
CPC分类号： H02M3/07
摘要： A regulator system includes first and second voltage sensing circuits coupled to a voltage generator control circuit. The first and second voltage sensing circuits are configured to monitor the voltage generated by the on-chip voltage generator (i.e., the on-chip supply voltage) and detect when the on-chip supply voltage reaches thresholds that are predetermined to define a desired range of the on-chip supply voltage. The voltage generator control circuit receives voltage sense signals from the voltage sense circuits and, in response, asserts or de-asserts a control signal received by the on-chip voltage generator so as to activate or de-activate the on-chip voltage generator to maintain the on-chip supply voltage within the desired range. The voltage generator control circuit introduces hysteresis in the generation of the control signal provided to the on-chip voltage generator. As a result of this hysteresis, once the on-chip voltage generator is activated, the voltage generator control circuit only de-activates the on-chip voltage generator when the on-chip supply voltage reaches the higher threshold. Conversely, once the on-chip voltage generator is de-activated, the voltage generator control circuit only activates the on-chip voltage generator when the on-chip supply voltage reaches the lower threshold.
摘要翻译： 调节器系统包括耦合到电压发生器控制电路的第一和第二电压感测电路。 第一和第二电压感测电路被配置为监视片上电压发生器产生的电压（即，片上电源电压），并且检测片上电源电压何时达到预定的阈值以限定期望的范围 的片上电源电压。 电压发生器控制电路接收来自电压检测电路的电压检测信号，并作为响应，断言或取消断言由片上电压发生器接收的控制信号，以激活或去激活片上电压发生器 将片上电源电压保持在所需范围内。 电压发生器控制电路在提供给片上电压发生器的控制信号的产生中引入滞后。 作为这种滞后的结果，一旦芯片上的电压发生器被激活，当片上电源电压达到较高的阈值时，电压发生器控制电路仅仅去激活片上电压发生器。 相反，一旦片上电压发生器被去激活，当片上电源电压达到较低阈值时，电压发生器控制电路仅激活片上电压发生器。
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10.发明授权Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor 失效具有可编程模式发生器的内存自检电路的存储器阵列，用于允许对相邻存储单元的唯一的读/写操作及其方法
公开(公告)号：US5790564A
公开(公告)日：1998-08-04
申请号：US485296
申请日：1995-06-07
CPC分类号： G11C29/36
摘要： An ABIST circuit for testing a memory array has a blanket write subcycle (WC), an RC3 subcycle, and an RC4 subcycle. The ABIST circuit includes a programmable pattern generator that provides eight programmable data bits, eight programmable read/write bits, and two programmable address frequency bits to determine the specific test patterns applied to the memory array. The address frequency bits determine how many memory cycles will be performed on each cell of the memory array. In X1 mode, only one memory cycle is performed on each cell during any given subcycle. In X2 mode, two memory cycles are performed on each cell, allowing a cell to be written, then subsequently read in the same subcycle. In X4 mode, four memory cycles are performed on each cell, and in X8 mode, all eight bits of read/write and data are used on each cell, resulting in eight memory cycles for each cell within the memory array.
摘要翻译： 用于测试存储器阵列的ABIST电路具有毯子写入子周期（WC），RC3子周期和RC4子周期。 ABIST电路包括一个可编程模式发生器，提供八个可编程数据位，八个可编程读/写位和两个可编程地址频率位，以确定应用于存储器阵列的特定测试模式。 地址频率位决定在存储器阵列的每个单元上执行多少个内存周期。 在X1模式下，在任何给定的子周期内，每个单元只执行一个存储周期。 在X2模式下，对每个单元执行两个存储周期，允许单元写入，然后在相同的子周期中读取。 在X4模式下，对每个单元执行四个存储周期，在X8模式下，每个单元都使用8位读/写和数据，从而为存储器阵列内的每个单元提供8个存储周期。
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