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1.发明授权Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor 失效具有可编程模式发生器的内存自检电路的存储器阵列，用于允许对相邻存储单元的唯一的读/写操作及其方法
公开(公告)号：US5790564A
公开(公告)日：1998-08-04
申请号：US485296
申请日：1995-06-07
CPC分类号： G11C29/36
摘要： An ABIST circuit for testing a memory array has a blanket write subcycle (WC), an RC3 subcycle, and an RC4 subcycle. The ABIST circuit includes a programmable pattern generator that provides eight programmable data bits, eight programmable read/write bits, and two programmable address frequency bits to determine the specific test patterns applied to the memory array. The address frequency bits determine how many memory cycles will be performed on each cell of the memory array. In X1 mode, only one memory cycle is performed on each cell during any given subcycle. In X2 mode, two memory cycles are performed on each cell, allowing a cell to be written, then subsequently read in the same subcycle. In X4 mode, four memory cycles are performed on each cell, and in X8 mode, all eight bits of read/write and data are used on each cell, resulting in eight memory cycles for each cell within the memory array.
摘要翻译： 用于测试存储器阵列的ABIST电路具有毯子写入子周期（WC），RC3子周期和RC4子周期。 ABIST电路包括一个可编程模式发生器，提供八个可编程数据位，八个可编程读/写位和两个可编程地址频率位，以确定应用于存储器阵列的特定测试模式。 地址频率位决定在存储器阵列的每个单元上执行多少个内存周期。 在X1模式下，在任何给定的子周期内，每个单元只执行一个存储周期。 在X2模式下，对每个单元执行两个存储周期，允许单元写入，然后在相同的子周期中读取。 在X4模式下，对每个单元执行四个存储周期，在X8模式下，每个单元都使用8位读/写和数据，从而为存储器阵列内的每个单元提供8个存储周期。
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公开(公告)号：US5745498A
公开(公告)日：1998-04-28
申请号：US661575
申请日：1996-06-11
IPC分类号： G01R31/26 , G01R31/28 , G01R31/3185 , G06F7/02 , G11C29/00 , G11C29/12 , G11C29/26 , G11C29/40 , G11C29/56 , H01L21/66 , G06F11/00
CPC分类号： G11C29/26 , G01R31/318527 , G06F7/02 , G11C29/40
摘要： A test method and structure is provided to determine the end count of a predetermined succession or series of binary numbers wherein one number and its relation in the succession to the end count number is known. The structure includes a circuit for generating a binary digit output and a device for storing at least a portion of the said one number which preferably is the penultimate number in a sequential series. A succession of binary numbers is generated as output of the circuit. the outputted numbers are compared to the portion of the stored number. A READY signal is outputted when the stored number compares with the outputted number. On a subsequent cycle, a control signal is generated when the generated number following the READY signal corresponds to the end count number. The inventor also contemplates programmable end count numbers.
摘要翻译： 提供了一种测试方法和结构来确定预定的一系列二进制数的结束计数，其中一个数目及其在终止计数序列中的关系是已知的。 该结构包括用于产生二进制数字输出的电路和用于存储所述一个数字的至少一部分的装置，其优选地是顺序序列中的倒数第二个数字。 产生一系列二进制数作为电路的输出。 将输出的数字与存储的数字的部分进行比较。 当存储的数字与输出的数字进行比较时，输出READY信号。 在随后的周期中，当READY信号之后的生成数字对应于结束计数号时，产生控制信号。 发明人还考虑了可编程的终端计数。
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公开(公告)号：US5740098A
公开(公告)日：1998-04-14
申请号：US671279
申请日：1996-06-27
申请人： Robert Dean Adams , John Connor , James J. Covino , Roy Childs Flaker , Garrett Stephen Koch , Alan Lee Roberts , Jose Roriz Sousa , Luigi Ternullo, Jr.
发明人： Robert Dean Adams , John Connor , James J. Covino , Roy Childs Flaker , Garrett Stephen Koch , Alan Lee Roberts , Jose Roriz Sousa , Luigi Ternullo, Jr.
IPC分类号： G06F12/16 , G06F12/08 , G11C8/10 , G11C15/00 , G11C15/04 , G11C29/00 , G11C29/02 , G11C29/10 , G11C29/12 , G11C29/56
CPC分类号： G11C29/12 , G06F12/0893 , G11C15/00 , G11C8/10 , G11C29/10
摘要： An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory. The second memory is then tested by generating inputs to the first memory during testing of the second memory. Thus, outputs of the first memory constitute at least a portion of test data inputted to the second memory. A latch is provided to capture the output of the test data from the second memory.
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4.发明授权Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor 失效具有可编程模式发生器的内存自检电路的存储器阵列，用于允许对相邻存储单元的唯一的读/写操作及其方法
公开(公告)号：US5771242A
公开(公告)日：1998-06-23
申请号：US721601
申请日：1996-09-25
CPC分类号： G11C29/36
摘要： An ABIST circuit for testing a memory array has a blanket write subcycle (WC), an RC.sub.3 subcycle, and an RC.sub.4 subcycle. The ABIST circuit includes a programmable pattern generator that provides eight programmable data bits, eight programmable read/write bits, and two programmable address frequency bits to determine the specific test patterns applied to the memory array. The address frequency bits determine how many memory cycles will be performed on each cell of the memory array. In X1 mode, only one memory cycle is performed on each cell during any given subcycle. In X2 mode, two memory cycles are performed on each cell, allowing a cell to be written, then subsequently read in the same subcycle, In X4 mode, four memory cycles are performed on each cell, and in Xg mode, all eight bits of read/write and data are used on each cell, resulting in eight memory cycles for each cell within the memory array.
摘要翻译： 用于测试存储器阵列的ABIST电路具有毯子写入子周期（WC），RC3子周期和RC4子周期。 ABIST电路包括一个可编程模式发生器，提供八个可编程数据位，八个可编程读/写位和两个可编程地址频率位，以确定应用于存储器阵列的特定测试模式。 地址频率位决定在存储器阵列的每个单元上执行多少个内存周期。 在X1模式下，在任何给定的子周期内，每个单元只执行一个存储周期。 在X2模式下，对每个单元执行两个存储周期，允许单元被写入，然后在相同的子周期中读取。在X4模式下，对每个单元执行四个存储周期，而在Xg模式下，所有8位 在每个单元上使用读/写和数据，从而为存储器阵列内的每个单元产生8个存储周期。
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5.发明授权Method and apparatus to determine erroneous value in memory cells using data compression 失效使用数据压缩来确定存储器单元中的错误值的方法和装置
公开(公告)号：US5761213A
公开(公告)日：1998-06-02
申请号：US603963
申请日：1996-02-20
IPC分类号： G01R31/26 , G01R31/28 , G01R31/3185 , G06F7/02 , G11C29/00 , G11C29/12 , G11C29/26 , G11C29/40 , G11C29/56 , H01L21/66
CPC分类号： G11C29/26 , G01R31/318527 , G06F7/02 , G11C29/40
摘要： A method and circuit are provided to detect if any bit stored in a given location in a memory is different from the data expected. The circuit includes logic to read each of the bits stored in the cells at given locations from memory and to generate a fail signal based on the data expected to be stored if the stored data is different from the expected data. The circuit also preferably includes logic to compare the True data and expect data read from each cell and generating the fail signal if they are the same. Additional logic circuitry is also preferably provided which determines if a node of the circuit remains in a precharged condition.
摘要翻译： 提供了一种方法和电路来检测存储在存储器中的给定位置中的任何位是否与预期的数据不同。 该电路包括从存储器中的给定位置读取存储在单元中的每个位的逻辑，并且如果存储的数据与预期数据不同，则基于预期存储的数据生成失败信号。 该电路还优选地包括用于比较True数据并期望从每个单元读取的数据的逻辑，并且如果它们相同则产生失败信号。 还优选地提供额外的逻辑电路，其确定电路的节点是否保持在预充电状态。
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公开(公告)号：US5784323A
公开(公告)日：1998-07-21
申请号：US795367
申请日：1997-02-04
IPC分类号： G06F12/16 , G11C29/02 , G11C29/12 , G11C29/14 , G11C29/16 , G11C29/36 , G11C29/38 , G11C29/00
摘要： The present invention provides a device for testing memory having write cycles and read cycles. A BIST state machine changes the data applied to the memory's DI port during read cycles to a value different from that of the data stored in the currently addressed memory location. The BIST-generated expect data also is at a different value from that of data at the memory's DI port and at the same value as the data stored at the current memory address location during read operations. With this arrangement, flush through defects can be detected which would not have been detectable by prior BIST machines.
摘要翻译： 本发明提供一种用于测试具有写周期和读周期的存储器的装置。 BIST状态机将读取周期期间应用于存储器的DI端口的数据更改为与存储在当前寻址的存储器位置中的数据不同的值。 BIST生成的期望数据也与存储器的DI端口的数据的值不同，并且在读操作期间与存储在当前存储器地址位置的数据相同。 通过这种布置，可以检测到冲洗缺陷，这是现有BIST机器不可检测的。
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公开(公告)号：US06353903B1
公开(公告)日：2002-03-05
申请号：US08330768
申请日：1994-10-28
IPC分类号： G01R3128
CPC分类号： G01R31/31926
摘要： True and complement data signals are provided to a multiplexer, which selects one of them based on a selection signal for capture by a single scannable latch in response to a clock signal. The scannable latch then provides the captured signal for testing by testing logic.
摘要翻译： 真和补补数据信号被提供给多路复用器，其根据选择信号选择它们中的一个，以响应于时钟信号由单个可扫描锁存器捕获。 可扫描锁存器然后提供捕获的信号，以便通过测试逻辑进行测试。
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公开(公告)号：US5535164A
公开(公告)日：1996-07-09
申请号：US398468
申请日：1995-03-03
IPC分类号： G01R31/26 , G01R31/28 , G01R31/3185 , G06F7/02 , G11C29/00 , G11C29/12 , G11C29/26 , G11C29/40 , G11C29/56 , H01L21/66 , G11C7/00
CPC分类号： G11C29/26 , G01R31/318527 , G06F7/02 , G11C29/40
摘要： The present invention, provides a single BIST which can test various memories of different sizes, types and characteristics by using a state machine to select and generate all patterns required for testing all of the memories on the chip, and impressing all of the data, including expected data, and address information on all of the memories simultaneously. The BIST also generates unique (separate) control signals for the various memories and impresses these control signals on the various memories. The BIST selectively asserts the various control signals so as to apply (write) the data and to read and capture (load result) failure information only to/from those memories whose unique controls are asserted. Selective assertion of a memory's write enable signal prevents multiple writes to a location which can potentially mask cell write and leakage defects while selective assertion of a memory's load result signal is performed only when valid memory output data is expected so as not to capture false error information. The control signals instruct those memories that do not use a particular sequence of inputs or any portion of a given sequence of inputs to "ignore" such signals, thereby generating the necessary signals to form the test patterns for each and every memory, the data and address information for those patterns, the control signals to write and read each memory, and capture error information for that particular memory. Hence, a single BIST can be used to test a multiplicity of memories of different sizes and different types.
摘要翻译： 本发明提供了一种可以通过使用状态机来选择和产生测试芯片上所有存储器所需的所有模式并且打印所有数据的不同尺寸，类型和特性的各种存储器，包括 预期数据和所有存储器的地址信息。 BIST还为各种存储器生成独特的（单独的）控制信号，并将这些控制信号印在各种存储器上。 BIST选择性地断言各种控制信号，以便仅对从其唯一控制被断言的那些存储器应用（写入）数据和仅读取和捕获（加载结果）故障信息。 存储器的写入使能信号的选择性断言防止对可能潜在地屏蔽单元写入和泄露缺陷的位置的多次写入，而只有在预期有效的存储器输出数据时执行存储器的负载结果信号的选择性断言，以便不捕获虚假错误信息 。 控制信号指示不使用特定输入序列或给定输入序列的任何部分的那些存储器“忽略”这样的信号，由此产生必要的信号以形成每个存储器的测试图案，数据和 这些模式的地址信息，用于写入和读取每个存储器的控制信号，以及捕获该特定存储器的错误信息。 因此，可以使用单个BIST来测试不同大小和不同类型的多个存储器。
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9.发明授权Memory array built-in self test circuit for testing multi-port memory arrays 失效内存阵列内置自检电路，用于测试多端口存储器阵列
公开(公告)号：US5796745A
公开(公告)日：1998-08-18
申请号：US684519
申请日：1996-07-19
CPC分类号： G11C29/20
摘要： A memory Array Built-In Self-Test (ABIST) circuit is disclosed that will test a multi-port memory array. A programmable pattern generator for the ABIST circuit allows for different R/W data operations to be performed at the same or adjacent address locations within a multi-port memory array. The programmable pattern generator comprises a data generator, a read/write controller, and an address counter, each having the same number of outputs as ports of the multi-port memory array. The programmable pattern generator also comprises a frequency controller. The data generator is programmed with the appropriate data patterns for the memory array, and the read/write controller is programmed with the appropriate read/write patterns for the memory array. The address counter is to provide the same or different addresses on each port of the multi-port array, and the frequency controller is programmed with the appropriate frequency information to determine the number of read/write operations per cell in the memory array. The combination of programmable data, programmable read/write sequences, programmable address counter, and programmable frequency allows for determistic testing of a multi-port memory array, a plurality of single-port memory arrays, or a combination thereof by providing unique read/write sequences to the same or to adjacent memory locations.
摘要翻译： 公开了一种内存自检（ABIST）电路，用于测试多端口存储器阵列。 用于ABIST电路的可编程模式发生器允许在多端口存储器阵列中的相同或相邻地址位置处执行不同的R / W数据操作。 可编程模式生成器包括数据发生器，读/写控制器和地址计数器，每个具有与多端口存储器阵列的端口相同数量的输出。 可编程模式发生器还包括频率控制器。 数据发生器用存储器阵列的适当数据模式进行编程，读/写控制器用适当的存储器阵列读/写模式进行编程。 地址计数器是在多端口阵列的每个端口上提供相同或不同的地址，并且频率控制器用适当的频率信息编程，以确定存储器阵列中每个单元的读/写操作的数量。 可编程数据，可编程读/写序列，可编程地址计数器和可编程频率的组合允许通过提供唯一的读/写来对多端口存储器阵列，多个单端口存储器阵列或其组合进行确定性测试 序列到相同或相邻的存储器位置。
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10.发明授权Using one memory to supply addresses to an associated memory during testing 失效在测试期间使用一个内存来提供地址给相关的内存
公开(公告)号：US5563833A
公开(公告)日：1996-10-08
申请号：US398465
申请日：1995-03-03
申请人： Robert D. Adams , John Connor , James J. Covino , Roy C. Flaker , Garrett S. Koch , Alan L. Roberts , Jose R. Sousa , Luigi Ternullo, Jr.
发明人： Robert D. Adams , John Connor , James J. Covino , Roy C. Flaker , Garrett S. Koch , Alan L. Roberts , Jose R. Sousa , Luigi Ternullo, Jr.
IPC分类号： G06F12/16 , G06F12/08 , G11C8/10 , G11C15/00 , G11C15/04 , G11C29/00 , G11C29/02 , G11C29/10 , G11C29/12 , G11C29/56 , G11C7/00
CPC分类号： G11C29/12 , G06F12/0893 , G11C15/00 , G11C8/10 , G11C29/10
摘要： An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory. The second memory is then tested by generating inputs to the first memory during testing of the second memory. Thus, outputs of the first memory constitute at least a portion of test data inputted to the second memory. A latch is provided to capture the output of the test data from the second memory.
摘要翻译： 提供了具有适于测试的多个存储器的关联存储器结构和测试存储器的方法。 形成第一和第二存储器，其中在两个存储器的功能操作期间，第一存储器中的数据为至少一部分输入提供基础。 优选地，提供用于从第一存储器接收输出测试数据的输出锁存器。 提供了用于将数据加载到第一存储器的装置，该数据被用作将至少一部分输入提供给第二存储器的基础。 从第一存储器的输出端口到第二存储器的输入端口的访问路径允许使用第一存储器中的数据来生成至第二存储器的输入的至少一部分。 第一个内存首先被独立于第二个内存进行测试。 此后，第一存储器加载预测数据，该预处理数据在第二存储器测试期间用作输入到第二存储器的基础。 然后在测试第二个存储器期间通过产生第一个存储器的输入来测试第二个存储器。 因此，第一存储器的输出构成输入到第二存储器的测试数据的至少一部分。 提供锁存器以捕获来自第二存储器的测试数据的输出。
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