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公开(公告)号：US20140379998A1
公开(公告)日：2014-12-25
申请号：US13922072
申请日：2013-06-19
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0817 , G06F2212/621 , Y02D10/13
摘要： Technologies for dynamic home tile mapping are described. an address request can be received from a processing core, the processing core being associated with a home tile table, the home tile table including respective mappings of one or more directory addresses to one or more home tiles. A buffer can be scanned to identify a presence of the address within the buffer. Based on an identification of the presence of the address within the buffer, a home tile identifier corresponding to the address can be provided from the buffer.
摘要翻译： 描述了用于动态家庭瓦片映射的技术。 可以从处理核心接收地址请求，处理核心与家庭瓦片表相关联，家庭瓦片表包括一个或多个目录地址到一个或多个家庭瓦片的各自的映射。 可以扫描缓冲区以识别缓冲区内存在的地址。 基于缓冲器中地址的存在的识别，可以从缓冲器提供对应于地址的归属瓦片标识符。
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2.发明申请公开(公告)号：US20150178086A1
公开(公告)日：2015-06-25
申请号：US14137218
申请日：2013-12-20
CPC分类号： G06F9/3806 , G06F9/3004 , G06F9/30087 , G06F9/382 , G06F9/3834 , G06F9/3836 , G06F11/0724 , G06F12/0806 , G06F12/0811 , G06F12/0842 , G06F12/0897 , G06F15/80
摘要： An apparatus and method for determining whether to execute an atomic operation locally or remotely. For example, one embodiment of a processor comprises: a decoder to decode an atomic operation on a local core; prediction logic on the local core to estimate a cost associated with execution of the atomic operation on the local core and a cost associated with execution of the atomic operation on a remote core; and the remote core to execute the atomic operation remotely if the prediction logic determines that the cost for execution on the local core is relatively greater than the cost for execution on the remote core; and the local core to execute the atomic operation locally if the prediction logic determines that the cost for local execution on the local core is relatively less than the cost for execution on the remote core.
摘要翻译： 一种用于确定是在本地还是远程执行原子操作的装置和方法。 例如，处理器的一个实施例包括：解码器，用于解码局部核心上的原子操作; 本地核心上的预测逻辑来估计与本地核心上的原子操作的执行相关的成本以及与在远程核心上执行原子操作相关联的成本; 以及所述远程核心，如果所述预测逻辑确定所述本地核上的执行成本相对大于所述远程核上的执行成本，则远程执行所述原子操作; 如果预测逻辑确定本地核心上的本地执行成本相对低于在远程核心上执行的成本，本地核心将在本地执行原子操作。
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公开(公告)号：US20140304477A1
公开(公告)日：2014-10-09
申请号：US13993034
申请日：2013-03-15
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/023 , G06F12/127 , Y02D10/13
摘要： A processing device comprises a processing device cache and a cache controller. The cache controller initiates a cache line eviction process and determines determine an object liveness value associated with a cache line in the processing device cache. The cache controller applies the object liveness value to a cache line eviction policy and evicts the cache line from the processing device cache based on the object liveness value and the cache line eviction policy.
摘要翻译： 处理设备包括处理设备高速缓存和高速缓存控制器。 高速缓存控制器启动高速缓存线驱逐过程并且确定确定与处理设备高速缓存中的高速缓存线相关联的对象活动值。 高速缓存控制器将对象活动值应用于高速缓存行驱逐策略，并基于对象活动性值和高速缓存行驱逐策略将缓存行从处理设备高速缓存中排除。
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公开(公告)号：US20150242210A1
公开(公告)日：2015-08-27
申请号：US14190404
申请日：2014-02-26
CPC分类号： G06F9/30036 , G06F9/30189 , G06F9/3887 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F2201/81 , G06F2201/88 , Y02D10/34
摘要： In an embodiment, a processor includes a vector execution unit having a plurality of lanes to execute operations on vector operands, a performance monitor coupled to the vector execution unit to maintain information regarding an activity level of the lanes, and a control logic coupled to the performance monitor to control power consumption of the vector execution unit based at least in part on the activity level of at least some of the lanes. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括具有多个通道以执行向量操作数的操作的向量执行单元，耦合到向量执行单元的性能监视器，以维护关于通道的活动级别的信息，以及耦合到该通道的控制逻辑 性能监视器，用于至少部分地基于至少一些车道的活动水平来控制向量执行单元的功率消耗。 描述和要求保护其他实施例。
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公开(公告)号：US20160179544A1
公开(公告)日：2016-06-23
申请号：US14580999
申请日：2014-12-23
摘要： A processor includes a core, a hardware prefetcher, and a prefetcher control module. The hardware prefetcher includes logic to make speculative prefetch requests, through a memory subsystem, for elements for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to selectively suppress, based on a hardware-prefetch suppression instruction executed by the core, a speculative prefetch request to be made by the hardware prefetcher.
摘要翻译： 处理器包括核心，硬件预取器和预取器控制模块。 硬件预取器包括用于通过存储器子系统进行推测预取请求的逻辑，用于由核心执行的元素以及将预取元素存储在高速缓存中的逻辑。 预取器控制模块包括用于基于由核心执行的硬件预取抑制指令来选择性地抑制由硬件预取器进行的推测预取请求的逻辑。
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6.发明申请公开(公告)号：US20140149718A1
公开(公告)日：2014-05-29
申请号：US13687918
申请日：2012-11-28
IPC分类号： G06F9/38
CPC分类号： G06F9/30043 , G06F9/30036 , G06F9/30185 , G06F9/3834 , G06F9/3851 , G06F9/3887 , G06F9/544 , G06F12/0815 , G06F12/084 , G06F12/0875 , G06F2212/452 , G06F2212/60 , G06F2212/621 , Y02D10/13
摘要： Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.
摘要翻译： 说明和逻辑提供推送缓冲区复制和存储功能。 一些实施例包括第一硬件线程或处理核心，以及第二硬件线程或处理核心，高速缓存，用于存储由第二硬件线程或处理核心可访问的共享存储器地址的高速缓存行中的高速缓存相干数据。 响应于对指定源数据操作数，所述共享存储器地址作为目的地操作数的指令以及所述共享存储器地址的一个或多个所有者进行解码，一个或多个执行单元将数据从源数据操作数复制到高速缓存一致数据 当所述一个或多个所有者包括所述第二硬件线程或处理核心时，由所述第二硬件线程或高速缓存中的处理核心访问的所述共享存储器地址的高速缓存行。
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7.发明申请公开(公告)号：US20180285280A1
公开(公告)日：2018-10-04
申请号：US15475249
申请日：2017-03-31
IPC分类号： G06F12/0888 , G06F12/0811
CPC分类号： G06F12/0888 , G06F12/04 , G06F12/0811 , G06F12/0831 , G06F12/0886 , G06F2212/1024 , G06F2212/1028 , G06F2212/283 , G06F2212/6046
摘要： In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.
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公开(公告)号：US20210004328A1
公开(公告)日：2021-01-07
申请号：US17027248
申请日：2020-09-21
申请人： Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
发明人： Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
IPC分类号： G06F12/0842 , G06F12/0831 , G06F12/0893 , G06F12/109 , G06F12/0813 , G06F9/455
摘要： Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.
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9.发明授权公开(公告)号：US09513905B2
公开(公告)日：2016-12-06
申请号：US12079774
申请日：2008-03-28
申请人： Mikhail Smelyanskiy , Sanjeev Kumar , Daehyun Kim , Jatin Chhugani , Changkyu Kim , Christopher J. Hughes , Victor W. Lee , Anthony D. Nguyen , Yen-Kuang Chen
发明人： Mikhail Smelyanskiy , Sanjeev Kumar , Daehyun Kim , Jatin Chhugani , Changkyu Kim , Christopher J. Hughes , Victor W. Lee , Anthony D. Nguyen , Yen-Kuang Chen
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/3885 , G06K9/6212 , G06T5/40 , H04N1/4074
摘要： In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.
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10.发明授权公开(公告)号：US08578097B2
公开(公告)日：2013-11-05
申请号：US13280117
申请日：2011-10-24
IPC分类号： G06F12/00
CPC分类号： G06F12/0806 , G06F12/08 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0862 , G06F12/0877 , G06F12/0891 , G06F12/0897 , G06F2212/6026 , G06F2212/62 , G11C7/1072 , G11C7/1075 , Y02D10/13
摘要： A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.
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