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1.发明授权Method of manufacturing semiconductor device comprising silicon-rich tasin metal gate electrode 有权一种制造半导体器件的方法，所述半导体器件包括富含硅的金属栅电极公开(公告)号：US06861350B1
公开(公告)日：2005-03-01
申请号：US10464508
申请日：2003-06-19
申请人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
发明人： Minh Van Ngo , Christy Mei-Chu Woo , Jinsong Yin , James Pan , Paul R. Besser
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H10L21/4763 , H10L21/44
CPC分类号： H01L29/66606 , H01L21/28088 , H01L29/4966 , H01L29/66545
摘要： Micro-miniaturized semiconductor devices are fabricated with silicon-rich tantalum silicon nitride replacement metal gate electrodes. Embodiments include removing a removable gate, depositing a layer of tantalum nitride, as by PVD at a thickness of 25 Å to 75 Å, and then introducing silicon into the deposited tantalum nitride layer by thermal soaking in silane or silane plasma treatment to form a layer of silicon-rich tantalum silicon nitride. In another embodiment, the intermediate structure is subjected to thermal soaking in silane or silane plasma treatment before and after depositing the tantalum nitride layer. Embodiments further include pretreating the intermediate structure with silane prior to depositing the tantalum nitride layer, treating the deposited tantalum nitride layer with silane, and repeating these steps a number of times to form a plurality of sub-layers of silicon-rich tantalum silicon nitride.
摘要翻译： 微型半导体器件由富含硅的钽氮化硅替代金属栅电极制成。 实施例包括去除可移除栅极，通过PVD沉积氮化钽层，厚度为25埃，然后通过在硅烷或硅烷等离子体处理中热浸泡形成层，将硅引入沉积的氮化钽层中 的富硅钽硅氮化物。 在另一个实施方案中，在沉积氮化钽层之前和之后，使中间体在硅烷或硅烷等离子体处理中进行热浸。 实施例还包括在沉积氮化钽层之前用硅烷预处理中间结构，用硅烷处理沉积的氮化钽层，并重复这些步骤多次以形成多个富硅钽硅氮化物的子层。
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2.发明授权公开(公告)号：US06893910B1
公开(公告)日：2005-05-17
申请号：US10462670
申请日：2003-06-17
申请人： Christy Mei-Chu Woo , Paul R. Besser , Minh Van Ngo , James N. Pan , Jinsong Yin
发明人： Christy Mei-Chu Woo , Paul R. Besser , Minh Van Ngo , James N. Pan , Jinsong Yin
IPC分类号： H01L21/28 , H01L21/316 , H01L21/336 , H01L29/49 , H01L29/51 , H01L29/78 , H01L21/338 , H01L21/31 , H01L21/3205
CPC分类号： H01L21/28185 , H01L21/28079 , H01L21/28194 , H01L21/31683 , H01L29/4958 , H01L29/511 , H01L29/517 , H01L29/66545 , H01L29/66583 , H01L29/7833
摘要： A method for forming a semiconductor structure removes the temporary gate formed on the dielectric layer to expose a recess in which oxygen-rich CVD oxide is deposited. A tantalum layer is then deposited by low-power physical vapor deposition on the CVD oxide. Annealing is then performed to create a Ta2O5 region and a Ta region from the deposited oxide and Ta. This creates a low carbon-content Ta2O5 and a metallic Ta gate in a single process step.
摘要翻译： 用于形成半导体结构的方法去除形成在电介质层上的临时栅极以暴露其中沉积有富氧CVD氧化物的凹槽。 然后通过低功率物理气相沉积在CVD氧化物上沉积钽层。 然后进行退火以从沉积的氧化物和Ta形成Ta 2 O 5区域和Ta区域。 这在单一工艺步骤中产生低碳含量的Ta 2 O 5 O 5和金属Ta浇口。
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公开(公告)号：US06661067B1
公开(公告)日：2003-12-09
申请号：US10260514
申请日：2002-10-01
IPC分类号： H01L2994
CPC分类号： H01L29/665 , H01L21/3115 , Y10S257/90
摘要： Bridging between nickel suicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.
摘要翻译： 通过用氮等离子体处理氮化硅侧壁间隔物的暴露表面来形成具有减少的游离硅的表面区域，防止栅电极上的硅化镍层与沿着氮化硅侧壁间隔物的源/漏区之间的桥接。 实施例包括用氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。
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4.发明授权Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing 有权使用一步快速热退火工艺和后端加工形成硅化镍的方法公开(公告)号：US06605513B2
公开(公告)日：2003-08-12
申请号：US09729699
申请日：2000-12-06
申请人： Eric N. Paton , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , George Jonathan Kluth , Minh Van Ngo , Christy Mei-Chu Woo
发明人： Eric N. Paton , Ercan Adem , Jacques J. Bertrand , Paul R. Besser , Matthew S. Buynoski , John Clayton Foster , Paul L. King , George Jonathan Kluth , Minh Van Ngo , Christy Mei-Chu Woo
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28061 , H01L21/28518 , H01L29/4933
摘要： A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.
摘要翻译： 自对准硅化物工艺，可以适应低热预算，并在受控反应中形成小尺寸的硅化物区域。 在第一温度处理中，镍金属或镍合金与硅材料反应以形成至少一个高电阻镍硅化物区域。 去除未反应的镍。 然后将电介质层沉积在高电阻镍硅化物区域上。 在第二温度处理中，至少一个高电阻镍硅化物区域和电介质层在规定温度下反应以形成至少一个低电阻硅化物区域并处理介电层。 通过控制硅化物生长的两步法避免区域之间的桥接，并且在第一温度处理之后去除硅化物区域之间的未反应的镍。 将高电阻镍硅化物区域和电介质层的处理方便地组合成单温度处理。
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公开(公告)号：US06465349B1
公开(公告)日：2002-10-15
申请号：US09679372
申请日：2000-10-05
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/3115 , Y10S257/90
摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by treating the exposed surfaces of the silicon nitride sidewall spacers with a nitrogen plasma to create a surface region having reduced free silicon. Embodiments include treating the silicon nitride sidewall spacers with a nitrogen plasma to reduce the refractive index of the surface region to less than about 1.95.
摘要翻译： 通过用氮等离子体处理氮化硅侧壁间隔物的暴露表面以形成具有减少的自由硅的表面区域，防止沿栅极电极的硅化镍层与氮化硅侧壁间隔物的源极/漏极区之间的桥接。 实施例包括用氮等离子体处理氮化硅侧壁间隔物以将表面区域的折射率降低到小于约1.95。
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6.发明授权Composite silicon nitride sidewall spacers for reduced nickel silicide bridging 有权用于还原硅化镍桥接的复合氮化硅侧壁间隔物公开(公告)号：US06545370B1
公开(公告)日：2003-04-08
申请号：US09679375
申请日：2000-10-05
IPC分类号： H01L27088
CPC分类号： H01L29/665 , H01L29/4983 , H01L29/6656
摘要： Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented by employing composite silicon nitride sidewall spacers comprising an outer layer having reduced free silicon. Embodiments include forming composite silicon nitride sidewall spacers comprising an inner silicon nitride layer, having a refractive index of about 1.95 to about 2.05 and a thickness of about 450 Å to about 550 Å, on the side surfaces of the gate electrode and an outer silicon nitride layer, having a refractive index to less than about 1.95 and a thickness of about 350 Å to about 450 Å.
摘要翻译： 通过使用复合氮化硅侧壁间隔物来防止在栅电极上的硅化镍层和沿着氮化硅侧壁间隔物的源极/漏极区之间的桥接，所述复合氮化硅侧壁间隔物包括具有减少的自由硅的外层。 实施例包括形成复合氮化硅侧壁间隔物，其包括内部氮化硅层，折射率为约1.95至约2.05，厚度约为450至大约的厚度在栅电极和外部氮化硅 层，具有小于约1.95的折射率和约350至约的厚度。
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公开(公告)号：US06372673B1
公开(公告)日：2002-04-16
申请号：US09781256
申请日：2001-02-13
IPC分类号： H01L21318
CPC分类号： H01L29/665 , H01L21/3185
摘要： Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming silicon-starved silicon nitride sidewall spacers having substantially no or significantly reduced Si available for reaction with deposited metal, e.g., nickel.
摘要翻译： 通过形成具有基本上没有或显着减少的Si的硅绝缘氮化硅侧壁间隔物来避免金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的桥接，可用于与沉积金属反应， 例如镍。
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公开(公告)号：US06387767B1
公开(公告)日：2002-05-14
申请号：US09781448
申请日：2001-02-13
IPC分类号： H01L21336
CPC分类号： H01L29/665
摘要： Salicide processing is implemented with nitrogen-rich silicon nitride sidewall spacers that allow a metal silicide layer e.g., NiSi, to be formed over the polysilicon gate electrode and source/drain regions using salicide technology without associated bridging between the metal silicide layer on the gate electrode and the metal silicide layers over the source/drain regions. Bridging between a metal silicide e.g., nickel silicide, layer on a gate electrode and metal silicide layers on associated source/drain regions is avoided by forming nitrogen-rich silicon nitride sidewall spacers with increased nitrogen, thereby eliminating free Si available to react with the metal subsequently deposited and thus avoiding the formation of metal silicide on the sidewall spacers.
摘要翻译： 使用富含氮的氮化硅侧壁间隔物实现自杀处理，其允许使用硅化物技术在多晶硅栅极电极和源极/漏极区域上形成金属硅化物层，例如NiSi，而不会在栅极上的金属硅化物层之间相互桥接 和源极/漏极区域之间的金属硅化物层。通过形成具有增加的富氮氮化硅侧壁间隔物，避免了金属硅化物（例如，硅化镍），栅极上的层和相关源极/漏极区域上的金属硅化物层之间的结合 氮，从而消除可用于随后沉积的金属的游离Si，从而避免在侧壁间隔物上形成金属硅化物。
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9.发明授权Semiconductor device with metal gate and high-k tantalum oxide or tantalum oxynitride gate dielectric 有权具有金属栅极和高k钽氧化物或氮氧化钽栅极电介质的半导体器件公开(公告)号：US07060571B1
公开(公告)日：2006-06-13
申请号：US10777138
申请日：2004-02-13
申请人： Minh Van Ngo , Christy Woo , James Pan , Paul R. Besser , Jinsong Yin
发明人： Minh Van Ngo , Christy Woo , James Pan , Paul R. Besser , Jinsong Yin
IPC分类号： H01L21/336
CPC分类号： H01L21/28229 , H01L21/28079 , H01L21/28088 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Microminiaturized semiconductor devices are fabricated with a replacement metal gate and a high-k tantalum oxide or tantalum oxynitride gate dielectric with significantly reduced carbon. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing a thin tantalum film, as by PVD at a thickness of 25 Å to 60 Å lining the opening, and then conducting thermal oxidation, as at a temperature of 100° C. to 500° C., in flowing oxygen or ozone to form a high-k tantalum oxide gate dielectric layer, or in oxygen and N2O or ozone and N2O ammonia to form a high-k tantalum oxynitride gate dielectric. Alternatively, oxidation can be conducted in an oxygen or ozone plasma to form the high-k tantalum oxide layer, or in a plasma containing N2O and oxygen or ozone to form the high-k tantalum oxynitride gate dielectric layer.
摘要翻译： 微型半导体器件由具有显着降低的碳的替代金属栅极和高k钽氧化物或氮氧化钽栅极电介质制成。 实施例包括通过去除可移除栅极来形成电介质层中的开口，沉积薄的钽膜，如通过PVD覆盖厚度为25埃至60埃的开口，然后在100℃的温度下进行热氧化 在500℃下，在流动的氧气或臭氧中形成高k氧化钽栅极电介质层，或在氧和N 2 O或臭氧和N 2 O 3 > O氨形成高k钽氮氧化物栅极电介质。 或者，可以在氧气或臭氧等离子体中进行氧化以形成高k钽氧化物层，或者在含有N 2 O的氧化物或臭氧的等离子体中进行氧化以形成高k氮氧化钽栅极 电介质层。
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10.发明授权公开(公告)号：US07217660B1
公开(公告)日：2007-05-15
申请号：US11109964
申请日：2005-04-19
IPC分类号： H01L21/22
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/28556 , H01L21/28562 , H01L21/76843 , H01L21/76846 , H01L29/6659
摘要： A method for manufacturing a semiconductor component that inhibits formation of wormholes in a semiconductor substrate. A contact opening is formed in a dielectric layer disposed on a semiconductor substrate. The contact opening exposes a portion of the semiconductor substrate. A sacrificial layer of oxide is formed on the exposed portion of the semiconductor substrate and along the sidewalls of the contact opening. Silane is reacted with tungsten hexafluoride to form a hydrofluoric acid vapor and tungsten. The hydrofluoric acid vapor etches away the sacrificial oxide layer and a thin layer of tungsten is formed on the exposed portion of the semiconductor substrate. After forming the thin layer of tungsten, the reactants may be changed to more quickly fill the contact opening with tungsten.
摘要翻译： 一种制造半导体元件的方法，该半导体元件抑制在半导体衬底中形成虫洞。 在设置在半导体衬底上的电介质层中形成接触开口。 接触开口露出半导体衬底的一部分。 在半导体衬底的暴露部分上并沿着接触开口的侧壁形成氧化物牺牲层。 硅烷与六氟化钨反应形成氢氟酸蒸汽和钨。 氢氟酸蒸气蚀刻掉牺牲氧化物层，并且在半导体衬底的暴露部分上形成薄的钨层。 在形成钨的薄层之后，可以改变反应物以更快地用钨填充接触开口。
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