公开(公告)号：US06407007B1

公开(公告)日：2002-06-18

申请号：US09193669

申请日：1998-11-17

申请人： Chun-Ching Tsan ,  Ying-Lang Wang ,  Hui-Ling Wang ,  Chin Kun Lan

发明人： Chun-Ching Tsan ,  Ying-Lang Wang ,  Hui-Ling Wang ,  Chin Kun Lan

IPC分类号： H01L21324

CPC分类号： H01L21/3185 ,  H01L21/316 ,  H01L21/76826

摘要： A method for improving the adhesion of a thick silicon nitride layer, to an underlying spin on glass, (SOG), layer, has been developed. After applying, baking and curing of a SOG layer, plasma treatment of the SOG layer, is performed in a deposition tool, using a nitrous oxide plasma. The plasma treatment prepares the exposed SOG surface for an in situ deposition of a thick silicon nitride layer, by improving the adhesion of thick silicon nitride to the underlying SOG layer, and by decreasing the possibility of silicon nitride delamination, that can occur with counterparts, fabricated without the nitrous oxide plasma treatment of the SOG layer.

摘要翻译： 已经开发了用于改善厚氮化硅层与玻璃上的底层旋涂（SOG）层的粘附性的方法。 施加，烘烤和固化SOG层之后，使用一氧化二氮等离子体在沉积工具中进行SOG层的等离子体处理。 等离子体处理通过改善厚氮化硅与下面的SOG层的粘附性以及通过降低可能与对应物发生的氮化硅分层的可能性来制备暴露的SOG表面，用于原位沉积厚的氮化硅层， 在没有氧化亚氮等离子体处理SOG层的情况下制造。

公开(公告)号：US6136680A

公开(公告)日：2000-10-24

申请号：US489498

申请日：2000-01-21

申请人： Jane-Bai Lai ,  Chung-Shi Liu ,  Tien-I Bao ,  Syun-Ming Jang ,  Chung-Long Chang ,  Hui-Ling Wang ,  Szu-An Wu ,  Wen-Kung Cheng ,  Chun-Ching Tsan ,  Ying-Lang Wang

发明人： Jane-Bai Lai ,  Chung-Shi Liu ,  Tien-I Bao ,  Syun-Ming Jang ,  Chung-Long Chang ,  Hui-Ling Wang ,  Szu-An Wu ,  Wen-Kung Cheng ,  Chun-Ching Tsan ,  Ying-Lang Wang

IPC分类号： H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76825 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/3212 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76883

摘要： A method of forming an interconnect, comprising the following steps. A semiconductor structure is provided that has an exposed first metal contact and a dielectric layer formed thereover. An FSG layer having a predetermined thickness is then formed over the dielectric layer. A trench, having a predetermined width, is formed within the FSG layer and the dielectric layer exposing the first metal contact. A barrier layer, having a predetermined thickness, may be formed over the FSG layer and lining the trench side walls and bottom. A metal, preferably copper, is then deposited on the barrier layer to form a copper layer, having a predetermined thickness, over said barrier layer covered FSG layer, filling the lined trench and blanket filling the barrier layer covered FSG layer. The copper layer, and the barrier layer on said upper surface of said FSG layer, are planarized, exposing the upper surface of the FSG layer and forming a planarized copper filled trench. The FSG layer and planarized copper filled trench are then processed by either: (1) annealing from about 400 to 450.degree. C. for about one hour, then either NH.sub.3 or H.sub.2 plasma treating; or (2) Ar.sup.+ sputtering to ion implant Ar.sup.+ to a depth of less than about 300 .ANG. in the fluorinated silica glass layer, whereby any formed Si--OH bonds and copper oxide (metal oxide) are removed. A dielectric cap layer, having a predetermined thickness, is then formed over the processed FSG layer and the planarized copper filled trench.

摘要翻译： 一种形成互连的方法，包括以下步骤。 提供一种半导体结构，其具有暴露的第一金属触点和形成在其上的电介质层。 然后在电介质层上形成具有预定厚度的FSG层。 具有预定宽度的沟槽形成在FSG层内，并且介电层露出第一金属接触。 具有预定厚度的阻挡层可以形成在FSG层之上并且衬在沟槽侧壁和底部。 然后将一种金属，优选铜沉积在阻挡层上，以形成具有预定厚度的铜层，超过所述阻挡层覆盖的FSG层，填充衬里的沟槽和覆盖填充阻挡层覆盖的FSG层的毯子。 所述FSG层的所述上表面上的铜层和阻挡层被平坦化，暴露出FSG层的上表面并形成平坦化的铜填充沟槽。 然后通过以下步骤之一处理FSG层和平坦化的铜填充沟槽：（1）从约400至450℃的退火约1小时，然后进行NH 3或H 2等离子体处理; 或者（2）在氟化石英玻璃层中，离子注入Ar +溅射至小于约300的深度，由此除去任何形成的Si-OH键和氧化铜（金属氧化物）。 然后在经处理的FSG层和平坦化的铜填充沟槽上形成具有预定厚度的电介质盖层。

公开(公告)号：US06287172B1

公开(公告)日：2001-09-11

申请号：US09465700

申请日：1999-12-17

申请人： Tong-Hua Kuan ,  Hui-Ling Wang ,  Ying-Lang Wang ,  Chin-Kun Lan

发明人： Tong-Hua Kuan ,  Hui-Ling Wang ,  Ying-Lang Wang ,  Chin-Kun Lan

IPC分类号： B24B100

CPC分类号： B24B37/345 ,  B24B37/0056 ,  B24B37/042 ,  B24D13/142

摘要： A multi-step chemical-mechanical polishing method for improving tungsten chemical-mechanical polishing (CMP) process is provided in the present invention. The method comprises following steps. First, a wafer is placed on a first pad of a CMP system, wherein a head fixes the wafer on the first pad. Then, the head is rotated and the wafer is polished on the first pad by using a tungsten slurry. Next, the wafer is transferred to place on a second pad of the CMP system, wherein the head fixes the wafer on the second pad. Following, the head is rotated and the wafer is polished on the second pad by using the tungsten slurry. Then, the wafer is cleaned on the second pad by using a de-ionic water. Next, the wafer is transferred to place on a third pad of the CMP system, wherein the head fixes the wafer on the third pad. Following, the wafer is cleaned on the third pad by using the de-ionic water. Last, the head is rotated and the wafer is polished on the third pad by using an oxide slurry, wherein a pH value of the tungsten slurry and a pH value of the oxide slurry are opposite.

摘要翻译： 本发明提供了一种用于改善钨化学机械抛光（CMP）工艺的多步化学机械抛光方法。 该方法包括以下步骤。 首先，将晶片放置在CMP系统的第一焊盘上，其中头部将晶片固定在第一焊盘上。 然后，头部旋转，并且通过使用钨浆料在第一焊盘上抛光晶片。 接下来，将晶片转移到CMP系统的第二焊盘上，其中头部将晶片固定在第二焊盘上。 接下来，头部旋转，并且通过使用钨浆料在第二垫上抛光晶片。 然后，通过使用脱离子水在第二焊盘上清洁晶片。 接下来，将晶片转移到CMP系统的第三焊盘上，其中头部将晶片固定在第三焊盘上。 接下来，通过使用去离子水在第三垫上清洁晶片。 最后，旋转头部，通过使用氧化物浆料在第三焊盘上抛光晶片，其中钨浆料的pH值和氧化物浆料的pH值相反。

公开(公告)号：US06399522B1

公开(公告)日：2002-06-04

申请号：US09075115

申请日：1998-05-11

申请人： Chun-Ching Tsan ,  Hung-Ju Chien ,  Chun-Chang Chen ,  Ying-Lang Wang

发明人： Chun-Ching Tsan ,  Hung-Ju Chien ,  Chun-Chang Chen ,  Ying-Lang Wang

IPC分类号： H01L2131

CPC分类号： H01L21/02164 ,  C23C16/02 ,  C23C16/402 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02312 ,  H01L21/31612

摘要： A method of forming a PE-silane oxide layer with a greatly reduced particle count is described. A semiconductor substrate is provided over which a silicon oxide film is to be formed. The silicon oxide film is formed by the steps of: 1) pre-flowing a non-silane gas into a deposition chamber for at least two seconds whereby the pre-flowing step prevents formation of particles on the silicon oxide film, and 2) thereafter depositing a silicon oxide film by chemical vapor deposition by flowing a silane gas into the deposition chamber to complete formation of a silicon oxide film using plasma-enhanced chemical vapor deposition in the fabrication of an integrated circuit.

摘要翻译： 描述了形成具有大大降低的粒子数的PE-硅烷氧化物层的方法。 提供半导体衬底，在其上形成氧化硅膜。 氧化硅膜是通过以下步骤形成的：1）将非硅烷气体预先流入沉积室至少两秒钟，由此预流步骤防止在氧化硅膜上形成颗粒，2）之后 通过将硅烷气体流入沉积室中，通过化学气相沉积来沉积氧化硅膜，以在集成电路的制造中使用等离子体增强化学气相沉积来形成氧化硅膜。

公开(公告)号：US06323141B1

公开(公告)日：2001-11-27

申请号：US09541485

申请日：2000-04-03

申请人： Szu-Au Wu ,  Chun-Ching Tsan ,  Wen-Kung Cheng ,  Ying-Lang Wang

发明人： Szu-Au Wu ,  Chun-Ching Tsan ,  Wen-Kung Cheng ,  Ying-Lang Wang

IPC分类号： H01L2131

CPC分类号： H01L21/3145 ,  C23C16/24 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/28123 ,  H01L21/31612 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for forming a patterned reflective layer first employs a substrate. There is then formed over the substrate a blanket reflective layer. There is then formed upon the blanket reflective layer an anti-reflective coating (ARC) layer formed employing a plasma enhanced chemical vapor deposition (PECVD) method employing a deposition gas composition comprising silane, nitrous oxide and argon. There is then formed upon the blanket anti-reflective coating (ARC) layer a blanket photoresist layer. There is then photoexposed and developed the blanket photoresist layer to form a patterned photoresist layer. There is then etched, while employing a first etch method, the blanket anti-reflective coating (ARC) layer to form a patterned anti-reflective coating (ARC) layer while employing the patterned photoresist layer as a first etch mask layer. Finally, there is then etched, while employing a second etch method, the blanket reflective layer to form the patterned reflective layer while employing at least the patterned anti-reflective coating (ARC) layer as a second etch mask layer.

摘要翻译： 用于形成图案化反射层的方法首先采用基板。 然后在衬底上形成覆盖层反射层。 然后在毯反射层上形成使用采用包含硅烷，一氧化二氮和氩的沉积气体组合物的等离子体增强化学气相沉积（PECVD）方法形成的抗反射涂层（ARC）层。 然后在橡皮布抗反射涂层（ARC）层上形成覆盖光致抗蚀剂层。 然后，将曝光的光刻胶照射并显影，以形成图案化的光致抗蚀剂层。 然后，在采用第一蚀刻方法的情况下，使用覆盖层抗反射涂层（ARC）层，同时使用图案化的光致抗蚀剂层作为第一蚀刻掩模层，来形成图案化的抗反射涂层（ARC）层。 最后，在采用第二蚀刻方法的同时，使用至少图案化的抗反射涂层（ARC）层作为第二蚀刻掩模层，同时使用第二蚀刻方法来蚀刻，以形成图案化的反射层。

公开(公告)号：US20080061343A1

公开(公告)日：2008-03-13

申请号：US11518470

申请日：2006-09-08

申请人： Chin Kun Lan ,  Sheng-Wen Chen ,  Hung Jui Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Chin Kun Lan ,  Sheng-Wen Chen ,  Hung Jui Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L29/94

CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A stacked metal-oxide-metal (MOM) capacitor structure and method of forming the same to increase an electrode/capacitor dielectric coupling area to increase a capacitance, the MOM capacitor structure including a plurality of metallization layers in stacked relationship; wherein each metallization layer includes substantially parallel spaced apart conductive electrode line portions having a first intervening capacitor dielectric; and, wherein the conductive electrode line portions are electrically interconnected between metallization layers by conductive damascene line portions formed in a second capacitor dielectric and disposed underlying the conductive electrode line portions.

摘要翻译： 一种堆叠的金属氧化物金属（MOM）电容器结构及其形成方法，以增加电极/电容器介质耦合面积以增加电容，所述MOM电容器结构包括堆叠关系的多个金属化层; 其中每个金属化层包括具有第一中间电容器电介质的基本上平行的隔开的导电电极线部分; 并且其中所述导电电极线部分通过形成在第二电容器电介质中并设置在所述导电电极线部分下方的导电镶嵌线部分在金属化层之间电互连。

公开(公告)号：US06268274B1

公开(公告)日：2001-07-31

申请号：US09418032

申请日：1999-10-14

申请人： Ying-Lang Wang ,  Chun-Ching Tsan ,  Jowei Dun ,  Hung-Ju Chien

发明人： Ying-Lang Wang ,  Chun-Ching Tsan ,  Jowei Dun ,  Hung-Ju Chien

IPC分类号： H01L2100

CPC分类号： H01L21/76801 ,  H01L21/31612 ,  H01L21/76837 ,  Y10S438/937

摘要： This invention provides an in situ low temperature, two step deposition HDP-CVD process separated by a cooldown period, for forming an inter-metal dielectric passivation layer for an integrated circuit structure. Said process mitigating metal line defects such as distortion or warping caused by excessive heat generated during the etching/deposition process.

摘要翻译： 本发明提供了一种在冷却期间分离的原位低温两步沉积HDP-CVD工艺，用于形成用于集成电路结构的金属间介电钝化层。 所述方法减轻金属线缺陷，例如在蚀刻/沉积工艺期间产生的过多热引起的变形或翘曲。

公开(公告)号：US07955993B2

公开(公告)日：2011-06-07

申请号：US12478493

申请日：2009-06-04

申请人： Chin Kun Lan ,  Sheng-Wen Chen ,  Hung Jui Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Chin Kun Lan ,  Sheng-Wen Chen ,  Hung Jui Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/31625 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/76826

摘要： A method including providing a semiconductor substrate in a reaction chamber; flowing a first reactant including silicon and oxygen, a boron dopant and a phosphorus dopant into the reaction chamber so that a layer of BPTEOS is deposited on the semiconductor substrate; stopping the flow of the first reactant, boron dopant and phosphorus dopant into the reaction chamber and so that a phosphorus dopant and boron dopant rich film is deposited over the layer of BPTEOS; and reducing the film comprising exposing the film to an O2 plasma.

摘要翻译： 一种包括在反应室中提供半导体衬底的方法; 将包括硅和氧的第一反应物，硼掺杂剂和磷掺杂剂流动到反应室中，使得在半导体衬底上沉积BPTEOS层; 阻止第一反应物，硼掺杂剂和磷掺杂剂流入反应室，使得磷掺杂剂和硼掺杂剂富含膜沉积在BPTEOS层上; 并且还原膜包括将膜暴露于O 2等离子体。

公开(公告)号：US20100311252A1

公开(公告)日：2010-12-09

申请号：US12478493

申请日：2009-06-04

申请人： Chin Kun Lan ,  Sheng-Wen Chen ,  Hung Jui Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

发明人： Chin Kun Lan ,  Sheng-Wen Chen ,  Hung Jui Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC分类号： H01L21/283 ,  H01L21/285

CPC分类号： H01L21/31625 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/76826

摘要： A method including providing a semiconductor substrate in a reaction chamber; flowing a first reactant including silicon and oxygen, a boron dopant and a phosphorus dopant into the reaction chamber so that a layer of BPTEOS is deposited on the semiconductor substrate; stopping the flow of the first reactant, boron dopant and phosphorus dopant into the reaction chamber and so that a phosphorus dopant and boron dopant rich film is deposited over the layer of BPTEOS; and reducing the film comprising exposing the film to an O2 plasma.

摘要翻译： 一种包括在反应室中提供半导体衬底的方法; 将包括硅和氧的第一反应物，硼掺杂剂和磷掺杂剂流动到反应室中，使得在半导体衬底上沉积BPTEOS层; 阻止第一反应物，硼掺杂剂和磷掺杂剂流入反应室，使得磷掺杂剂和富含硼的掺杂剂的膜沉积在BPTEOS层上; 并且还原膜包括将膜暴露于O 2等离子体。

公开(公告)号：US06645825B1

公开(公告)日：2003-11-11

申请号：US09614554

申请日：2000-07-12

申请人： Chin Kun Lan ,  Ting Chun Wang ,  Tong-Hua Kuan ,  Ying-Lang Wang

发明人： Chin Kun Lan ,  Ting Chun Wang ,  Tong-Hua Kuan ,  Ying-Lang Wang

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： An improved and new process for fabricating a planarized structure of shallow trench isolation (STI) embedded in a silicon substrate has been developed. The planarizing method comprises a two-step CMP process in which the first CMP step comprises chemical-mechanical polishing of silicon oxide using a first polishing slurry which is selective to silicon oxide. The time of the second CMP step is determined by selecting an overpolish thickness based on the percentage of substrate area occupied by the trench. High manufacturing yield and superior planarity for silicon oxide STI are achieved.

摘要翻译： 已经开发了一种用于制造嵌入硅衬底中的浅沟槽隔离（STI）的平面化结构的改进和新工艺。 平面化方法包括两步CMP工艺，其中第一CMP步骤包括使用对氧化硅选择性的第一抛光浆料进行二氧化硅的化学机械抛光。 通过基于沟槽占据的衬底面积的百分比来选择过抛光厚度来确定第二CMP步骤的时间。 实现了高的制造成品率和优异的氧化硅STI平坦度。