公开(公告)号：US08659349B1

公开(公告)日：2014-02-25

申请号：US13626630

申请日：2012-09-25

申请人： Colin Lyden ,  Donal Bourke ,  Dennis A. Dempsey ,  Dermot G. O'Keeffe ,  Patrick Kirby

发明人： Colin Lyden ,  Donal Bourke ,  Dennis A. Dempsey ,  Dermot G. O'Keeffe ,  Patrick Kirby

IPC分类号： G06G7/12

CPC分类号： G01N27/028 ,  G01N27/3273 ,  G01N27/49 ,  H03F1/34 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2200/462 ,  H03L5/00

摘要： A control circuit for use with a four terminal sensor, the sensor having first and second drive terminals and first and second measurement terminals, the control circuit arranged to drive at least one of the first and second drive terminals with an excitation signal, to sense a voltage difference between the first and second measurement terminals, and control the excitation signal such that the voltage difference between the first and second measurement terminals is within a target range of voltages, and wherein the control circuit includes N poles in its transfer characteristic and N−1 zeros in its transfer characteristic such that when a loop gain falls to unity the phase shift around a closed loop is not substantially 2π radians or a multiple thereof, where N is greater than 1.

摘要翻译： 一种与四端子传感器一起使用的控制电路，所述传感器具有第一和第二驱动端子以及第一和第二测量端子，所述控制电路被布置成用激励信号驱动第一和第二驱动端子中的至少一个，以感测 并且控制所述激励信号，使得所述第一测量端子与所述第二测量端子之间的电压差在目标电压范围内，并且其中所述控制电路在其传输特性中包括N极，并且所述N- 1的零传递特性使得当环路增益下降到1时，围绕闭环的相移基本上不是2pi弧度或其倍数，其中N大于1。

公开(公告)号：US20070296618A1

公开(公告)日：2007-12-27

申请号：US11474174

申请日：2006-06-23

申请人： Gavin Cosgrave ,  Colin Gerard Lyden ,  Roderick C. McLachlan ,  Dennis A. Dempsey ,  Tudor M. Vinereanu ,  Patrick Kirby

发明人： Gavin Cosgrave ,  Colin Gerard Lyden ,  Roderick C. McLachlan ,  Dennis A. Dempsey ,  Tudor M. Vinereanu ,  Patrick Kirby

IPC分类号： H03M1/66

CPC分类号： H03M1/1038 ,  H03M1/662 ,  H03M1/68

摘要： The invention provides a multi-channel DAC circuit which provides for correlation between selected ones of the multiple channels such that a single set of calibration coefficients may be used for calibration of multiple channels.

摘要翻译： 本发明提供一种多通道DAC电路，其提供多个通道中的选定的通道之间的相关性，使得可以使用单组校准系数来校准多个通道。

公开(公告)号：US07339508B2

公开(公告)日：2008-03-04

申请号：US11474174

申请日：2006-06-23

申请人： Gavin Cosgrave ,  Colin Gerard Lyden ,  Roderick C. McLachlan ,  Dennis A. Dempsey ,  Tudor M. Vinereanu ,  Patrick Kirby

发明人： Gavin Cosgrave ,  Colin Gerard Lyden ,  Roderick C. McLachlan ,  Dennis A. Dempsey ,  Tudor M. Vinereanu ,  Patrick Kirby

IPC分类号： H03M1/06

CPC分类号： H03M1/1038 ,  H03M1/662 ,  H03M1/68

摘要： The invention provides a multi-channel DAC circuit which provides for correlation between selected ones of the multiple channels such that a single set of calibration coefficients may be used for calibration of multiple channels.

摘要翻译： 本发明提供一种多通道DAC电路，其提供多个通道中的选定的通道之间的相关性，使得可以使用单组校准系数来校准多个通道。

公开(公告)号：US20060061500A1

公开(公告)日：2006-03-23

申请号：US11048374

申请日：2005-02-01

申请人： Patrick Kirby ,  Colin Lyden ,  Tudor Vinereanu

发明人： Patrick Kirby ,  Colin Lyden ,  Tudor Vinereanu

IPC分类号： H03M1/66

CPC分类号： H03M1/1057 ,  H03M1/785

摘要： A DAC architecture is described. The architecture is specifically adapted to provided an analog voltage output based on a digital input word. The architecture includes a resistor ladder configuration sub-divisible into a first component, adapted to convert a lower part of the input word, and a second component adapted to convert an upper part of the input word. The DAC is calibrated such that the first component can be used to tune the output of the second component on selection of specific segment from the second component.

公开(公告)号：US5076804A

公开(公告)日：1991-12-31

申请号：US618549

申请日：1990-11-27

申请人： Dominique Bertho ,  Richard Donnelly ,  Patrick Kirby

发明人： Dominique Bertho ,  Richard Donnelly ,  Patrick Kirby

IPC分类号： H01R12/58 ,  H01R12/83 ,  H01R24/00 ,  H05K3/30

CPC分类号： H01R12/58 ,  H01R12/83 ,  H05K3/308 ,  H05K2201/10189 ,  H05K2201/10787 ,  H05K2201/10878

摘要： An electrical connector assembly is provided for mounting on a printed circuit board which includes at least a pair of mounting post-receiving holes and at least one solder tail-receiving aperture. The assembly includes a housing having at least a pair of mounting posts for positioning in the holes in the printed circuit board. At least one contact member is mounted on the housing and includes a solder tail for positioning in the aperture in the printed circuit board. The solder tail has a generally straight side and a projecting hook on an opposite side for retaining the connector assembly on the printed circuit board. The width of the solder tail between the straight side and the outermost point of the hook on the opposite side is no greater than the width of the aperture, and the centerline of the solder tail between its sides is offset, in the direction of the hook, relative to the centerline of the aperture when the mounting posts are aligned with the holes in the printed circuit board.

公开(公告)号：US20050122170A1

公开(公告)日：2005-06-09

申请号：US10728053

申请日：2003-12-04

申请人： Patrick Kirby

发明人： Patrick Kirby

IPC分类号： H03F1/32 ,  H03F3/45

CPC分类号： H03F3/45475 ,  H03F1/3211 ,  H03F3/45183 ,  H03F3/45982

摘要： A circuit (1) comprising eight DACs (2a to 2h), the analog outputs of which are applied to the non-inverting inputs (6) of corresponding op-amps (7a to 7h) for gaining up the analog output voltage from the corresponding DAC (2). The op-amps (7) are identical, and are configured in a non-inverting mode with a closed loop gain of two provided by first and second resistors (R1) and (R2). Primary outputs (8) of the op-amps (7) are coupled to output pins (9a to 9h) of the circuit (1). The second resistors (R2) couple primary inverting inputs (12) of the op-amps (7) to a common voltage reference rail (14), which is coupled to a true ground reference pin (15) through a coupling wire (16) which exhibit a combined inherent resistance (Rp). The voltage reference on the common voltage reference rail (14) varies with time as the output signals of the op-amps (7) vary, and would thus result in cross-talk between the DACs (2a to 2h). Each op-amp (7) comprises a secondary differential input amplifier stage (36), the non-inverting and inverting inputs (37,38) of which are coupled to the common voltage reference rail (14) and the ground reference pin (15), respectively. The secondary differential input stage (36) provides a secondary current to a node (29) in the op-amp (7) in response to variation in the time varying voltage reference for summing with an intermediate current provided through the node (29) by a primary differential input amplifier stage (25) of the op-amp (7) for correcting the output voltage signal on the primary output (8) for variation in the voltage reference on the common voltage reference rail (14).

公开(公告)号：US06198313B1

公开(公告)日：2001-03-06

申请号：US09082032

申请日：1998-05-20

申请人： Patrick F. M. Poucher ,  Patrick Kirby ,  Christopher A. Kenny ,  Donal Geraghty

发明人： Patrick F. M. Poucher ,  Patrick Kirby ,  Christopher A. Kenny ,  Donal Geraghty

IPC分类号： G11C2702

CPC分类号： G11C27/02

摘要： An infinite sample-and-hold circuit which employs a DAC and an ADC coupled with a mode control circuit. In acquisition mode, the mode control circuit connects the analog input signal to the ADC. The ADC drives the DAC and when the DAC output equals the analog input, the mode control circuit disconnects the analog input and the DAC drives the output in hold mode. The mode control circuit preferably includes a comparator/buffer circuit including switching circuitry. The ADC is preferably of the successive approximation type. The comparator/buffer is used in two modes: (1) open loop, as a comparator, and (2) closed loop, as a buffer. During acquisition, the comparator mode is used, while in hold mode the buffer mode is used. The utilization of the same amplifier to provide both functions allows cancellation of offset errors otherwise introduced by the comparator and buffer, at least to a first order.

摘要翻译： 无限采样保持电路，采用DAC和ADC耦合模式控制电路。 在采集模式下，模式控制电路将模拟输入信号连接到ADC。 ADC驱动DAC，当DAC输出等于模拟输入时，模式控制电路断开模拟输入，DAC在保持模式下驱动输出。 模式控制电路优选地包括包括开关电路的比较器/缓冲器电路。 ADC优选地是逐次逼近型。 比较器/缓冲器用于两种模式：（1）开环，比较器和（2）闭环作为缓冲器。 在采集期间，使用比较器模式，而在保持模式下，使用缓冲模式。 使用相同的放大器来提供两个功能允许消除比较器和缓冲器否则引入的偏移错误，至少是第一级。

公开(公告)号：US06570517B1

公开(公告)日：2003-05-27

申请号：US09858932

申请日：2001-05-16

申请人： Donal Geraghty ,  Patrick Kirby

发明人： Donal Geraghty ,  Patrick Kirby

IPC分类号： H03M100

CPC分类号： H03M1/662

摘要： A multi-channel DAC having a digital input port (2) for receiving digital input codes and a plurality of analogue output terminals (OUT1 to OUTN) on channels (CH1 to CHN) on which corresponding analogue signals are outputted, comprises a primary DAC (3) which receives the digital input codes from the input port (2). Analogue signals from the primary DAC (3) are selectively and sequentially sampled onto infinite sample and hold circuits (SH1 to SHN) of the channel (CH1 to CHN) through primary switches PS1 to PSN) under the control of a primary control circuit (5). Each infinite sample and hold circuit (SH1 to SHN) comprises a secondary DAC (10) which outputs an analogue signal which closely approximates to the sampled analogue signal from the primary DAC (3) and which is held on the corresponding output terminal (OUT1 to OUTN). Secondary digital codes may be selectively applied to the secondary DACs 10 of the respective infinite sample and hold circuits SH1 to SHN for incrementing or decrementing the analogue signal held on the corresponding output (OUT1 to OUTN).

摘要翻译： 具有用于接收数字输入代码的数字输入端口（2）和在其上输出相应的模拟信号的通道（CH1至CHN）上的多个模拟输出端子（OUT1至OUTN）的多通道DAC包括主DAC（ 3），其从输入端口（2）接收数字输入代码。 在主控制电路（5）的控制下，来自主DAC（3）的模拟信号被选择性地并顺序地采样到通道（CH1至CHN）的无限取样和保持电路（SH1至SHN）上，通过初级开关PS1至PSN） ）。 每个无限取样和保持电路（SH1至SHN）包括二次DAC（10），该二次DAC（10）输出一个模拟信号，该模拟信号与初级DAC（3）的采样模拟信号非常相似，并保持在相应的输出端（OUT1至 OUTN）。 可以将辅助数字码选择性地施加到相应的无限取样和保持电路SH1至SHN的辅助DAC 10，以增加或减少保持在相应输出（OUT1至OUTN）上的模拟信号。