公开(公告)号：US11876090B2

公开(公告)日：2024-01-16

申请号：US17989481

申请日：2022-11-17

Applicant: Cypress Semiconductor Corporation

Inventor： David Michael Rogers ,  Eric N. Mann ,  Eric Lee Swindlehurst ,  Toru Miyamae ,  Timothy John Williams ,  Ryuta Nagai ,  Sungkwon Lee ,  Ravindra M. Kapre ,  Mimi Xuefeng Zhao Qian ,  Yan Yi ,  Dung Si Ho ,  Boo Chin-Hua

IPC: H01L27/02

CPC classification number: H01L27/0285 ,  H01L27/0288

Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

公开(公告)号：US20230343779A1

公开(公告)日：2023-10-26

申请号：US17989481

申请日：2022-11-17

Applicant: Cypress Semiconductor Corporation

Inventor： David Michael Rogers ,  Eric N. Mann ,  Eric Lee Swindlehurst ,  Toru Miyamae ,  Timothy John Williams ,  Ryuta Nagai ,  Sungkwon Lee ,  Ravindra M. Kapre ,  Mimi Xuefeng Zhao Qian ,  Yan Yi ,  Dung Si Ho ,  Boo Chin-Hua

IPC: H01L27/02

CPC classification number: H01L27/0285 ,  H01L27/0288

Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

公开(公告)号：US11251805B2

公开(公告)日：2022-02-15

申请号：US17072697

申请日：2020-10-16

Applicant: Cypress Semiconductor Corporation

Inventor： Eashwar Thiagarajan ,  Erhan Hancioglu ,  Eric N. Mann ,  Harold Kutz ,  Amsby D Richardson, Jr. ,  Rajiv Singh

IPC: H03M1/00 ,  H03M1/18 ,  H03G3/30

Abstract: A method can include modulating an amplified analog signal into a digital data stream, filtering the digital data stream with a first filter, generating gain control values associated with amplified analog signal based on the filtered data stream with the first filter and filtering the digital data stream with a second filter, and generating output digital values associated with the amplified analog signal based on the filtered data stream with the second filter. Corresponding systems and devices are also disclosed.

公开(公告)号：US09692442B1

公开(公告)日：2017-06-27

申请号：US15387337

申请日：2016-12-21

Applicant: Cypress Semiconductor Corporation

Inventor： Harold M. Kutz ,  Erhan Hancioglu ,  Timothy John Williams ,  Hans Klein ,  Eric N. Mann

IPC: H03M1/10 ,  H03M1/66 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/181 ,  H03M1/00 ,  H03M1/004 ,  H03M1/12 ,  H03M1/124 ,  H03M1/785

Abstract: A device, system, and method of a programmable circuit configured to operate in a buffered drive mode and blanking mode is disclosed. The programmable circuit includes a continuous-time digital-to-analog converter (CTDAC), a continuous-time block (CTB), coupled to the CTDAC, and a sample and hold (SH) circuit coupled to the CTDAC and the CTB. The programmable circuit is configured to operate in a buffered drive mode to buffer an output signal from the CTDAC. The programmable circuit, in buffered drive mode, is further configured to operate in a blanking mode to cause the SH circuit to perform a blanking operation on the CTDAC output signal.

公开(公告)号：US11521962B1

公开(公告)日：2022-12-06

申请号：US17475303

申请日：2021-09-14

Applicant: Cypress Semiconductor Corporation

Inventor： David Michael Rogers ,  Eric N. Mann ,  Eric Lee Swindlehurst ,  Toru Miyamae ,  Timothy John Williams ,  Ryuta Nagai ,  Sungkwon Lee ,  Ravindra M. Kapre ,  Mimi Xuefeng Zhao Qian ,  Yan Yi ,  Dung Si Ho ,  Boo Chin-Hua

IPC: H01L27/02

Abstract: An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

公开(公告)号：US20210409034A1

公开(公告)日：2021-12-30

申请号：US17072697

申请日：2020-10-16

Applicant: Cypress Semiconductor Corporation

Inventor： Eashwar Thiagarajan ,  Erhan Hancioglu ,  Eric N. Mann ,  Harold Kutz ,  Amsby D. Richardson, JR. ,  Rajiv Singh

IPC: H03M1/18 ,  H03G3/30

Abstract: A method can include modulating an amplified analog signal into a digital data stream, filtering the digital data stream with a first filter, generating gain control values associated with amplified analog signal based on the filtered data stream with the first filter and filtering the digital data stream with a second filter, and generating output digital values associated with the amplified analog signal based on the filtered data stream with the second filter. Corresponding systems and devices are also disclosed.

公开(公告)号：US11496148B2

公开(公告)日：2022-11-08

申请号：US17242728

申请日：2021-04-28

Applicant: Cypress Semiconductor Corporation

Inventor： Eric N. Mann ,  Erhan Hancioglu ,  Eashwar Thiagarajan ,  Harold Kutz ,  Amsby D Richardson, Jr.

IPC: H03M3/00 ,  H03M1/06 ,  H03M1/18

Abstract: One or more systems and/or methods for implementing an analog-to-digital converter system with a floating digital channel configuration are provided. An analog input component is configured to receive measured analog signals, and output analog signals, corresponding to the measured analog signals, to an analog channel coupled to the analog input component. The analog channel is coupled to a switching component connected to a first digital channel and a second digital channel. The analog channel comprises a modulator configured to convert the analog signals into a data stream selectively input by the switching component to the first digital channel or the second digital channel.

公开(公告)号：US20220302925A1

公开(公告)日：2022-09-22

申请号：US17242728

申请日：2021-04-28

Applicant: Cypress Semiconductor Corporation

Inventor： Eric N. Mann ,  Erhan Hancioglu ,  Eashwar Thiagarajan ,  Harold Kutz ,  Amsby D Richardson, JR.

IPC: H03M3/00 ,  H03M1/18 ,  H03M1/06

Abstract: One or more systems and/or methods for implementing an analog-to-digital converter system with a floating digital channel configuration are provided. An analog input component is configured to receive measured analog signals, and output analog signals, corresponding to the measured analog signals, to an analog channel coupled to the analog input component. The analog channel is coupled to a switching component connected to a first digital channel and a second digital channel. The analog channel comprises a modulator configured to convert the analog signals into a data stream selectively input by the switching component to the first digital channel or the second digital channel.