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    CMOS integration scheme employing a silicide electrode and a silicide-germanide alloy electrode
    1.
    发明授权
    CMOS integration scheme employing a silicide electrode and a silicide-germanide alloy electrode 失效
    CMOS集成方案采用硅化物电极和硅化锗 - 锗化物合金电极

    公开(公告)号：US07749847B2

    公开(公告)日：2010-07-06

    申请号：US12031224

    申请日：2008-02-14

    申请人： Cyril Cabral, Jr. ,  Jack O. Chu ,  Young-Hee Kim

    发明人： Cyril Cabral, Jr. ,  Jack O. Chu ,  Young-Hee Kim

    IPC分类号： H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/823835 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4933 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  Y10S438/933

    摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) are formed by patterning of a gate dielectric layer, a thin silicon layer, and a silicon-germanium alloy layer. After formation of the source/drain regions and gate spacers, silicon germanium alloy portions are removed from gate stacks. A dielectric layer is formed and patterned to cover an NFET gate electrode, while exposing a thin silicon portion for a PFET. Germanium is selectively deposited on semiconductor surfaces including the exposed silicon portion. The dielectric layer is removed and a metal layer is deposited and reacted with underlying semiconductor material to form a metal silicide for a gate electrode of the NFET, while forming a metal silicide-germanide alloy for a gate electrode of the PFET.

    摘要翻译： 通过构图栅极电介质层，薄硅层和硅 - 锗合金层来形成p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 在形成源极/漏极区域和栅极间隔物之后，从栅极叠层去除硅锗合金部分。 形成介电层并图案化以覆盖NFET栅电极，同时暴露用于PFET的薄硅部分。 锗选择性地沉积在包括暴露的硅部分的半导体表面上。 去除电介质层，并沉积金属层并与下面的半导体材料反应以形成用于NFET的栅电极的金属硅化物，同时形成用于PFET的栅电极的金属硅化物 - 锗化物合金。

    CMOS INTEGRATION SCHEME EMPLOYING A SILICIDE ELECTRODE AND A SILICIDE-GERMANIDE ALLOY ELECTRODE
    2.
    发明申请
    CMOS INTEGRATION SCHEME EMPLOYING A SILICIDE ELECTRODE AND A SILICIDE-GERMANIDE ALLOY ELECTRODE 失效
    使用硅酮电极和硅锗合金电极的CMOS集成方案

    公开(公告)号：US20090206413A1

    公开(公告)日：2009-08-20

    申请号：US12031224

    申请日：2008-02-14

    申请人： Cyril Cabral, JR. ,  Jack O. Chu ,  Young-Hee Kim

    发明人： Cyril Cabral, JR. ,  Jack O. Chu ,  Young-Hee Kim

    IPC分类号： H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/823835 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4933 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  Y10S438/933

    摘要： A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) are formed by patterning of a gate dielectric layer, a thin silicon layer, and a silicon-germanium alloy layer. After formation of the source/drain regions and gate spacers, silicon germanium alloy portions are removed from gate stacks. A dielectric layer is formed and patterned to cover an NFET gate electrode, while exposing a thin silicon portion for a PFET. Germanium is selectively deposited on semiconductor surfaces including the exposed silicon portion. The dielectric layer is removed and a metal layer is deposited and reacted with underlying semiconductor material to form a metal silicide for a gate electrode of the NFET, while forming a metal silicide-germanide alloy for a gate electrode of the PFET.

    摘要翻译： 通过构图栅极电介质层，薄硅层和硅 - 锗合金层来形成p型场效应晶体管（PFET）和n型场效应晶体管（NFET）。 在形成源极/漏极区域和栅极间隔物之后，从栅极叠层去除硅锗合金部分。 形成介电层并图案化以覆盖NFET栅电极，同时暴露用于PFET的薄硅部分。 锗选择性地沉积在包括暴露的硅部分的半导体表面上。 去除电介质层，并沉积金属层并与下面的半导体材料反应以形成用于NFET的栅电极的金属硅化物，同时形成用于PFET的栅电极的金属硅化物 - 锗化物合金。

    Method for low temperature selective growth of silicon or silicon alloys
    3.
    发明授权
    Method for low temperature selective growth of silicon or silicon alloys 失效
    硅或硅合金的低温选择性生长方法

    公开(公告)号：US5565031A

    公开(公告)日：1996-10-15

    申请号：US390132

    申请日：1995-02-17

    申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

    发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

    IPC分类号： C30B29/06 ,  C23C14/08 ,  C23C16/04 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205

    CPC分类号： H01L21/02642 ,  H01L21/02373 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02631 ,  Y10S148/106 ,  Y10S438/945

    摘要： Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.

    摘要翻译： 通过在晶片上形成选自钪，钇，镧，铈，镨，钕，钕，钕等的元素的氧化物的薄膜掩蔽层，选择性地在半导体衬底或晶片上生长硅和硅 - 锗合金的外延和多晶层， 钐，铕，钆，铽，镝，钬，铒，ium，镱和镥; 然后在低于650℃的温度下在晶片上生长外延层。外延层和多晶层不会在掩模层上生长。 本发明克服了通过提供较低温度的工艺在高于650℃的温度下形成外延层的问题。

    Low temperature selective growth of silicon or silicon alloys
    6.
    发明授权
    Low temperature selective growth of silicon or silicon alloys 失效
    硅或硅合金的低温选择性生长

    公开(公告)号：US5634973A

    公开(公告)日：1997-06-03

    申请号：US587029

    申请日：1996-01-16

    申请人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

    发明人： Cyril Cabral, Jr. ,  Kevin K. Chan ,  Jack O. Chu ,  James M. E. Harper

    IPC分类号： C30B29/06 ,  C23C14/08 ,  C23C16/04 ,  H01L21/20 ,  H01L21/203 ,  H01L21/205 ,  C30B33/06

    CPC分类号： H01L21/02642 ,  H01L21/02373 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02631 ,  Y10S148/106 ,  Y10S438/945

    摘要： Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.

    摘要翻译： 通过在晶片上形成选自钪，钇，镧，铈，镨，钕，钕，钕等的元素的氧化物的薄膜掩蔽层，选择性地在半导体衬底或晶片上生长硅和硅 - 锗合金的外延和多晶层， 钐，铕，钆，铽，镝，钬，铒，ium，镱和镥; 然后在低于650℃的温度下在晶片上生长外延层。外延层和多晶层不会在掩模层上生长。 本发明克服了通过提供较低温度的工艺在高于650℃的温度下形成外延层的问题。

    Suspended germanium photodetector for silicon waveguide
    9.
    发明授权
    Suspended germanium photodetector for silicon waveguide 有权
    用于硅波导的悬浮锗光电探测器

    公开(公告)号：US07902620B2

    公开(公告)日：2011-03-08

    申请号：US12191687

    申请日：2008-08-14

    申请人： Solomon Assefa ,  Jack O. Chu ,  Martin M. Frank ,  William M. Green ,  Young-hee Kim ,  George G. Totir ,  Joris Van Campenhout ,  Yurii A. Vlasov ,  Ying Zhang

    发明人： Solomon Assefa ,  Jack O. Chu ,  Martin M. Frank ,  William M. Green ,  Young-hee Kim ,  George G. Totir ,  Joris Van Campenhout ,  Yurii A. Vlasov ,  Ying Zhang

    IPC分类号： H01L31/18

    CPC分类号： H01L31/1804 ,  B82Y20/00 ,  G02B6/12004 ,  G02B6/136 ,  G02B2006/12123 ,  H01L31/109 ,  H01L31/1812 ,  Y02E10/547 ,  Y02P70/521

    摘要： A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.

    摘要翻译： 在第一外延硅层的顶表面上外延地形成第一硅锗合金层，第二外延硅层，第二硅锗层和锗层的垂直叠层。 第二外延硅层，第二硅锗层和锗层通过介电盖部分，电介质间隔物和第一硅锗层被图案化和封装。 在第一和第二硅层之间移除硅锗层以形成硅锗台面结构，其结构上支撑包括硅部分，硅锗合金部分，锗光电检测器和介电帽部分的叠层的悬垂结构。 锗光电探测器由硅锗台面结构悬挂而不邻接硅波导。 锗扩散到硅波导和锗检测器中的缺陷密度被最小化。