CMOS integration scheme employing a silicide electrode and a silicide-germanide alloy electrode
    1.
    发明授权
    CMOS integration scheme employing a silicide electrode and a silicide-germanide alloy electrode 失效
    CMOS集成方案采用硅化物电极和硅化锗 - 锗化物合金电极

    公开(公告)号:US07749847B2

    公开(公告)日:2010-07-06

    申请号:US12031224

    申请日:2008-02-14

    IPC分类号: H01L21/8238 H01L27/092

    摘要: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) are formed by patterning of a gate dielectric layer, a thin silicon layer, and a silicon-germanium alloy layer. After formation of the source/drain regions and gate spacers, silicon germanium alloy portions are removed from gate stacks. A dielectric layer is formed and patterned to cover an NFET gate electrode, while exposing a thin silicon portion for a PFET. Germanium is selectively deposited on semiconductor surfaces including the exposed silicon portion. The dielectric layer is removed and a metal layer is deposited and reacted with underlying semiconductor material to form a metal silicide for a gate electrode of the NFET, while forming a metal silicide-germanide alloy for a gate electrode of the PFET.

    摘要翻译: 通过构图栅极电介质层,薄硅层和硅 - 锗合金层来形成p型场效应晶体管(PFET)和n型场效应晶体管(NFET)。 在形成源极/漏极区域和栅极间隔物之后,从栅极叠层去除硅锗合金部分。 形成介电层并图案化以覆盖NFET栅电极,同时暴露用于PFET的薄硅部分。 锗选择性地沉积在包括暴露的硅部分的半导体表面上。 去除电介质层,并沉积金属层并与下面的半导体材料反应以形成用于NFET的栅电极的金属硅化物,同时形成用于PFET的栅电极的金属硅化物 - 锗化物合金。

    CMOS INTEGRATION SCHEME EMPLOYING A SILICIDE ELECTRODE AND A SILICIDE-GERMANIDE ALLOY ELECTRODE
    2.
    发明申请
    CMOS INTEGRATION SCHEME EMPLOYING A SILICIDE ELECTRODE AND A SILICIDE-GERMANIDE ALLOY ELECTRODE 失效
    使用硅酮电极和硅锗合金电极的CMOS集成方案

    公开(公告)号:US20090206413A1

    公开(公告)日:2009-08-20

    申请号:US12031224

    申请日:2008-02-14

    IPC分类号: H01L21/8238 H01L27/092

    摘要: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) are formed by patterning of a gate dielectric layer, a thin silicon layer, and a silicon-germanium alloy layer. After formation of the source/drain regions and gate spacers, silicon germanium alloy portions are removed from gate stacks. A dielectric layer is formed and patterned to cover an NFET gate electrode, while exposing a thin silicon portion for a PFET. Germanium is selectively deposited on semiconductor surfaces including the exposed silicon portion. The dielectric layer is removed and a metal layer is deposited and reacted with underlying semiconductor material to form a metal silicide for a gate electrode of the NFET, while forming a metal silicide-germanide alloy for a gate electrode of the PFET.

    摘要翻译: 通过构图栅极电介质层,薄硅层和硅 - 锗合金层来形成p型场效应晶体管(PFET)和n型场效应晶体管(NFET)。 在形成源极/漏极区域和栅极间隔物之后,从栅极叠层去除硅锗合金部分。 形成介电层并图案化以覆盖NFET栅电极,同时暴露用于PFET的薄硅部分。 锗选择性地沉积在包括暴露的硅部分的半导体表面上。 去除电介质层,并沉积金属层并与下面的半导体材料反应以形成用于NFET的栅电极的金属硅化物,同时形成用于PFET的栅电极的金属硅化物 - 锗化物合金。

    Buried selective emitter formation for photovoltaic devices utilizing metal nanoparticle catalyzed etching
    4.
    发明授权
    Buried selective emitter formation for photovoltaic devices utilizing metal nanoparticle catalyzed etching 失效
    用于利用金属纳米颗粒催化蚀刻的光伏器件的掩埋式选择性发射极形成

    公开(公告)号:US08759139B2

    公开(公告)日:2014-06-24

    申请号:US13212740

    申请日:2011-08-18

    IPC分类号: H01L31/18

    摘要: A method of forming a photovoltaic device containing a buried emitter region and vertical metal contacts is provided. The method includes forming a plurality of metal nanoparticles on exposed portions of a single-crystalline silicon substrate that are not covered by patterned antireflective coatings (ARCs). A metal nanoparticle catalyzed etching process is then used to form trenches within the single-crystalline silicon substrate and thereafter the metal nanoparticles are removed from the trenches. An emitter region is then formed within exposed portions of the single-crystalline silicon substrate, and thereafter a metal contact is formed atop the emitter region.

    摘要翻译: 提供一种形成包含掩埋发射极区域和垂直金属触点的光伏器件的方法。 该方法包括在未被图案化抗反射涂层(ARC)覆盖的单晶硅衬底的暴露部分上形成多个金属纳米颗粒。 然后使用金属纳米颗粒催化的蚀刻工艺在单晶硅衬底内形成沟槽,此后从沟槽中去除金属纳米颗粒。 然后在单晶硅衬底的暴露部分内形成发射极区域,然后在发射极区域的顶部形成金属接触。

    METHOD FOR FERMENTING ANTLERS, VENISON, OR DEER BONES USING MUSHROOMS, AND RESULTANT FERMENTED PRODUCTS
    5.
    发明申请
    METHOD FOR FERMENTING ANTLERS, VENISON, OR DEER BONES USING MUSHROOMS, AND RESULTANT FERMENTED PRODUCTS 审中-公开
    使用FOR FOR FOR TING AN AN AN PRODUCTS PRODUCTS PRODUCTS PRODUCTS PRODUCTS PRODUCTS PRODUCTS PRODUCTS PRODUCTS PRODUCTS PRODUCTS PRODUCTS PRODUCTS PRODUCTS PRODUCTS

    公开(公告)号:US20140017333A1

    公开(公告)日:2014-01-16

    申请号:US14003539

    申请日:2012-02-24

    IPC分类号: A61K35/32 C12P1/02

    摘要: The present invention relates to a method of fermenting velvet antler (or venison or deer bone) together with a mushroom concentration in order to increase the efficacy thereof, and a fermentation product obtained thereby. In accordance with the present invention, velvet antler is fermented in a state in which it was not concentrated or ground, and the shape thereof is maintained after fermentation. Thus, the loss of velvet antler is insignificant, and the fermented velvet antler has a high efficacy and can be used in various shapes in subsequent processes.

    摘要翻译: 本发明涉及一种将天鹅绒鹿茸(或鹿肉或鹿骨)与蘑菇浓度一起发酵以提高其功效的方法,以及由此获得的发酵产物。 根据本发明,天鹅绒鹿茸在未浓缩或研磨的状态下发酵,发酵后保持其形状。 因此,天鹅绒鹿茸的损失是微不足道的,发酵天鹅绒鹿茸具有高效率,并且可以在后续过程中以各种形状使用。

    DUAL TRANSPARENT CONDUCTIVE MATERIAL LAYER FOR IMPROVED PERFORMANCE OF PHOTOVOLTAIC DEVICES
    7.
    发明申请
    DUAL TRANSPARENT CONDUCTIVE MATERIAL LAYER FOR IMPROVED PERFORMANCE OF PHOTOVOLTAIC DEVICES 审中-公开
    双色透明导电材料层,用于改进光伏器件的性能

    公开(公告)号:US20110308585A1

    公开(公告)日:2011-12-22

    申请号:US12816745

    申请日:2010-06-16

    摘要: A dual transparent conductive material layer is provided between a p-doped semiconductor layer and a substrate layer of a photovoltaic device. The dual transparent conductive material layer includes a first transparent conductive material and a second transparent conductive material wherein the second transparent conductive material is nano-structured. The nano-structured second transparent conductive material acts as a protective layer for the underlying first transparent conductive material. The nano-structured transparent conductive material provides a benefit of a higher Eg of the underlying first transparent conductive material surface and a very high resilience to hydrogen plasma from the nano-structures during the formation of the p-doped semiconductor layer.

    摘要翻译: 在p掺杂半导体层和光伏器件的衬底层之间提供双透明导电材料层。 双透明导电材料层包括第一透明导电材料和第二透明导电材料,其中第二透明导电材料是纳米结构的。 纳米结构的第二透明导电材料用作下面的第一透明导电材料的保护层。 纳米结构的透明导电材料提供了下面的第一透明导电材料表面的更高等价的优点,以及在形成p掺杂半导体层期间来自纳米结构的氢等离子体的非常高的回弹性。

    Self-diagnosis arrangement for a video display and method of implementing the same
    9.
    再颁专利
    Self-diagnosis arrangement for a video display and method of implementing the same 有权
    视频显示器的自诊断方案及其实现方法

    公开(公告)号:USRE38537E1

    公开(公告)日:2004-06-22

    申请号:US09401485

    申请日:1999-09-22

    申请人: Young-Hee Kim

    发明人: Young-Hee Kim

    IPC分类号: G09G108

    摘要: A self-diagnostic arrangement for a video display apparatus and method effectuating the same is disclosed. The apparatus according to the present invention includes a cable connector, amplifiers and a cathode ray tube and comprises a microprocessor storing information on a display status, for selectively switching signals to generate horizontal and vertical sync signals for displaying a variety of self-diagnostic displays, an on screen display IC for supplying a blanking signal and a video signal correspondingly responsive to information supplied from the microprocessor and a H/V deflection circuit for supplying on screen display video. signals to the CRT. There is also provided a method of self-diagnosis, which comprises the steps of generating internal horizontal and vertical sync.signals sync signals of predetermined frequency levels and displaying self-diagnostic screens representing video component colors and a display status.

    Self-diagnosis arrangement for a video display and method of
implementing the same
    10.
    发明授权
    Self-diagnosis arrangement for a video display and method of implementing the same 失效
    视频显示器的自诊断方案及其实现方法

    公开(公告)号:US5670972A

    公开(公告)日:1997-09-23

    申请号:US546865

    申请日:1995-10-23

    申请人: Young-Hee Kim

    发明人: Young-Hee Kim

    摘要: A self-diagnostic arrangement for a video display apparatus and method effectuating the same is disclosed. The apparatus according to the present invention includes a cable connector, amplifiers and a cathode ray tube and comprises a microprocessor storing information on a display status, for selectively switching signals to generate horizontal and vertical sync signals for displaying a variety of self-diagnostic displays, an on screen display IC for supplying a blanking signal and a video signal correspondingly responsive to information supplied from the microprocessor and a H/V deflection circuit for supplying on screen display video. signals to the CRT. There is also provided a method of self-diagnosis, which comprises the steps of generating internal horizontal and vertical sync.signals of predetermined frequency levels and displaying self-diagnostic screens representing video component colors and a display status.

    摘要翻译: 公开了一种用于视频显示装置的自诊断装置和实现其的方法。 根据本发明的装置包括电缆连接器,放大器和阴极射线管,并且包括存储关于显示状态的信息的微处理器,用于选择性地切换信号以产生用于显示各种自诊断显示器的水平和垂直同步信号, 用于提供相应于从微处理器提供的信息的消隐信号和视频信号的屏幕显示IC和用于提供屏幕显示视频的H / V偏转电路。 信号到CRT。 还提供了一种自诊断方法,其包括以下步骤:产生预定频率水平的内部水平和垂直同步信号,并且显示表示视频分量颜色和显示状态的自诊断屏幕。