摘要:
An internal control signal regulation circuit includes a programming test unit configured to detect an internal control signal in response to an external control signal and generate a selection signal, test codes and a programming enable signal; and a code processing unit configured to receive the test codes or programming codes in response to the selection signal and regulate the internal control signal.
摘要:
A clock generating circuit of a semiconductor memory apparatus includes a phase splitter that delays a clock to generate a delayed clock and inverts the clock to generate an inverted clock, and a clock buffer that buffers the delayed clock and the inverted clock and outputs a rising clock and a falling clock.
摘要:
The present invention discloses an on die termination circuit. The on die termination circuit used in a DDR2 employs transmission gates as pull-up and pull-down switches, equalizes pull-up and pull-down resistance values by changing connection relations between switches and resistors, and maintains a constant voltage of an input pin.
摘要:
The data output circuit for a semiconductor memory apparatus includes a first control signal generating unit configured to generate a first control signal according to a row address and a read command; and a data selecting unit configured to select data from a data line corresponding to a presently selected unit data output mode among data lines according to the first control signal or a second control signal, and output the data.
摘要:
A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal.
摘要:
The data output circuit for a semiconductor memory apparatus includes a first control signal generating unit configured to generate a first control signal according to a row address and a read command; and a data selecting unit configured to select data from a data line corresponding to a presently selected unit data output mode among data lines according to the first control signal or a second control signal, and output the data.
摘要:
A semiconductor memory apparatus includes a PLL selector that selectively activates a plurality of PLL enable signals by decoding pluralities of PLL selection signals, and a plurality of PLL circuits that connect to a plurality of PLL enable signals respectively, wherein when the one of a plurality of PLL enable signals is activated, the PLL circuit connected the activated PLL enable signal is operated to execute phase locking operations.
摘要:
A semiconductor apparatus includes a power supply changing unit. The power supply changing unit is configured to receive an enable signal and power supply voltage, generate first voltage or second voltage according to the enable signal, change a voltage level of the second voltage according to a level signal, and supply the first voltage or the second voltage as a driving voltage of an internal circuit, wherein the internal circuit receives a first input signal to output a second input signal.
摘要:
An output driver includes: a pull-up signal generation unit configured to control a pulse width of first data and output a pull-up pre-drive signal; a pull-down signal generation unit configured to control a pulse width of second data and output a pull-down pre-drive signal; a pull-up pre-driver unit configured to receive the pull-up pre-drive signal and generate a pull-up main drive signal; a pull-down pre-driver unit configured to receive the pull-down pre-drive signal and generate a pull-down main drive signal; a pull-up main driver unit configured to charge an output node according to the pull-up main drive signal; and a pull-down main driver unit configured to discharge the output node according to the pull-down main drive signal.
摘要:
Disclosed is a semiconductor device capable of detecting levels of an external supply voltage, which includes a plurality of signal receivers for simultaneously receiving external input signals, wherein a driving voltage is applied to only one of the signal receivers according to the levels of the external supply voltage.