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    Method of fabricating static random access memory
    1.
    发明授权
    Method of fabricating static random access memory 有权
    制造静态随机存取存储器的方法

    公开(公告)号：US07598141B2

    公开(公告)日：2009-10-06

    申请号：US11261266

    申请日：2005-10-28

    申请人： Chang-Hoon Lee ,  Sang-Jin Park ,  Won-Seok Yoo ,  Kong-Soo Lee

    发明人： Chang-Hoon Lee ,  Sang-Jin Park ,  Won-Seok Yoo ,  Kong-Soo Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11 ,  H01L27/1104

    摘要： A method of fabricating a static random access memory device includes selectively removing an insulating film and growing a single crystalline silicon layer using selective epitaxy growth, the single crystalline silicon layer being grown in a portion from which the insulating film is removed; recessing the insulating film; and depositing an amorphous silicon layer on the single crystalline silicon layer and the insulating film, such that the amorphous silicon layer partially surrounds a top surface and side surfaces of the single crystalline silicon layer.

    摘要翻译： 一种制造静态随机存取存储器件的方法包括：使用选择性外延生长选择性地去除绝缘膜并生长单晶硅层，单晶硅层在除去绝缘膜的部分中生长; 使绝缘膜凹陷; 以及在所述单晶硅层和所述绝缘膜上沉积非晶硅层，使得所述非晶硅层部分地包围所述单晶硅层的顶表面和侧表面。

    Methods of forming integrated circuit devices having vertical semiconductor interconnects and diodes therein and devices formed thereby
    3.
    发明授权
    Methods of forming integrated circuit devices having vertical semiconductor interconnects and diodes therein and devices formed thereby 有权
    形成其中具有垂直半导体互连和二极管的集成电路器件的方法及由此形成的器件

    公开(公告)号：US08119503B2

    公开(公告)日：2012-02-21

    申请号：US12498528

    申请日：2009-07-07

    申请人： Kong-Soo Lee ,  Kyoung-Seok Kim ,  Sang-Jin Park ,  Chang-Hoon Lee ,  Ji-Hyun Jeong ,  Jae-Hyun Park ,  Jae-Hee Oh

    发明人： Kong-Soo Lee ,  Kyoung-Seok Kim ,  Sang-Jin Park ,  Chang-Hoon Lee ,  Ji-Hyun Jeong ,  Jae-Hyun Park ,  Jae-Hee Oh

    IPC分类号： H01L47/00 ,  H01L21/20

    CPC分类号： H01L27/1021 ,  H01L27/24 ,  H01L29/8613

    摘要： Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer.

    摘要翻译： 形成集成电路器件的方法包括在半导体衬底的表面上形成蚀刻停止层，并在蚀刻停止层上形成第一层间绝缘层。 图案化第一层间绝缘层以限定其中暴露出蚀刻停止层的第一部分的开口。 然后去除蚀刻停止层的第一部分，从而暴露半导体衬底的表面的下面部分。 蚀刻停止层的这种去除可以通过使用磷酸溶液湿蚀刻蚀刻停止层的第一部分来进行。 然后使用半导体衬底的表面的暴露部分作为外延种子层，选择性地将半导体区域生长到开口中。

    Methods of Forming Integrated Circuit Devices Having Vertical Semiconductor Interconnects and Diodes Therein and Devices Formed Thereby
    4.
    发明申请
    Methods of Forming Integrated Circuit Devices Having Vertical Semiconductor Interconnects and Diodes Therein and Devices Formed Thereby 有权
    形成具有垂直半导体互连和二极管的集成电路器件的方法和由此形成的器件

    公开(公告)号：US20100108971A1

    公开(公告)日：2010-05-06

    申请号：US12498528

    申请日：2009-07-07

    申请人： Kong-Soo Lee ,  Kyoung-Seok Kim ,  Sang-Jin Park ,  Chang-Hoon Lee ,  Ji-Hyun Jeong ,  Jae-Hyun Park ,  Jae-Hee Oh

    发明人： Kong-Soo Lee ,  Kyoung-Seok Kim ,  Sang-Jin Park ,  Chang-Hoon Lee ,  Ji-Hyun Jeong ,  Jae-Hyun Park ,  Jae-Hee Oh

    IPC分类号： H01L47/00 ,  H01L21/20

    CPC分类号： H01L27/1021 ,  H01L27/24 ,  H01L29/8613

    摘要： Methods of forming integrated circuit devices include forming an etch stop layer on a surface of a semiconductor substrate and forming a first interlayer insulating layer on the etch stop layer. The first interlayer insulating layer is patterned to define an opening therein that exposes a first portion of the etch stop layer. This first portion of the etch stop layer is then removed to thereby expose an underlying portion of the surface of the semiconductor substrate. This removal of the etch stop layer may be performed by wet etching the first portion of the etch stop layer using a phosphoric acid solution. A semiconductor region is then selectively grown into the opening, using the exposed portion of the surface of the semiconductor substrate as an epitaxial seed layer.

    摘要翻译： 形成集成电路器件的方法包括在半导体衬底的表面上形成蚀刻停止层，并在蚀刻停止层上形成第一层间绝缘层。 图案化第一层间绝缘层以限定其中暴露出蚀刻停止层的第一部分的开口。 然后去除蚀刻停止层的第一部分，从而暴露半导体衬底的表面的下面部分。 蚀刻停止层的这种去除可以通过使用磷酸溶液湿蚀刻蚀刻停止层的第一部分来进行。 然后使用半导体衬底的表面的暴露部分作为外延种子层，选择性地将半导体区域生长到开口中。

    Stacked semiconductor devices and methods of manufacturing the same
    7.
    发明授权
    Stacked semiconductor devices and methods of manufacturing the same 失效
    叠层半导体器件及其制造方法

    公开(公告)号：US08039900B2

    公开(公告)日：2011-10-18

    申请号：US11823765

    申请日：2007-06-28

    申请人： Kyoung-Seok Kim ,  Kong-Soo Lee ,  Sang-Jin Park ,  Sung-Kwan Kang ,  Ko-Eun Lee

    发明人： Kyoung-Seok Kim ,  Kong-Soo Lee ,  Sang-Jin Park ,  Sung-Kwan Kang ,  Ko-Eun Lee

    IPC分类号： H01L29/66

    CPC分类号： H01L27/0688 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28556 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/8221 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108

    摘要： The stacked semiconductor device includes a semiconductor substrate, a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, an active layer pattern formed on each of the insulation layer patterns, a first plug including single crystalline silicon-germanium, a second plug including single crystalline silicon, and a wiring electrically connected to the first plug and sufficiently filling up the opening. The insulation layer patterns are vertically stacked on the semiconductor substrate and the opening exposes an upper face of the semiconductor substrate. A side portion of the active layer pattern is exposed by the opening. The first plug is formed on the upper face of the semiconductor substrate to partially fill the opening. The second plug is partially formed on the first plug, and has substantially the same interface as that of the first plug.

    摘要翻译： 叠层半导体器件包括半导体衬底，具有至少两个绝缘层图案和开口的多层绝缘层图案，形成在每个绝缘层图案上的有源层图案，包括单晶硅锗的第一插头， 包括单晶硅的第二插头和电连接到第一插头并充分填满开口的布线。 绝缘层图案垂直堆叠在半导体衬底上，并且开口暴露半导体衬底的上表面。 有源层图案的侧面部分由开口露出。 第一插头形成在半导体衬底的上表面上以部分地填充开口。 第二插头部分地形成在第一插头上，并且具有与第一插头基本相同的界面。