公开(公告)号：US5115289A

公开(公告)日：1992-05-19

申请号：US742196

申请日：1991-08-05

申请人： Dai Hisamoto ,  Toru Kaga ,  Shinichiro Kimura ,  Masahiro Moniwa ,  Haruhiko Tanaka ,  Atsushi Hiraiwa ,  Eiji Takeda

发明人： Dai Hisamoto ,  Toru Kaga ,  Shinichiro Kimura ,  Masahiro Moniwa ,  Haruhiko Tanaka ,  Atsushi Hiraiwa ,  Eiji Takeda

IPC分类号： H01L21/336 ,  H01L21/339 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/108 ,  H01L27/11 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L21/76264 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10879 ,  H01L27/1108 ,  H01L29/1062 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66954 ,  H01L29/78654 ,  H01L21/76278

摘要： A semiconductor device, such as an FET or a charge coupled device, is provided having a channel or a charge coupled portion formed in a thin semiconductor layer which is substantially perpendicular to the substrate. Necessary electrodes, such as the gate electrode, and necessary insulating layers can be added at the thin semiconductor layer, and can maintain the necessary amount of electric current by securing the height of the semiconductor layer. The structure has the advantage that it can have its plane size reduced. Further, the semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics.

摘要翻译： 提供了诸如FET或电荷耦合器件的半导体器件，其具有形成在基本上垂直于衬底的薄半导体层中的沟道或电荷耦合部分。 可以在薄的半导体层添加必要的电极，例如栅电极和必要的绝缘层，并且可以通过确保半导体层的高度来保持必要的电流量。 该结构具有能够减小其平面尺寸的优点。 此外，使用上述半导体器件的半导体存储器件适合于高集成度并且具有优异的电特性。

公开(公告)号：US5466621A

公开(公告)日：1995-11-14

申请号：US141027

申请日：1993-10-25

申请人： Dai Hisamoto ,  Toru Kaga ,  Shinichiro Kimura ,  Masahiro Moniwa ,  Haruhiko Tanaka ,  Atsushi Hiraiwa ,  Eiji Takeda

发明人： Dai Hisamoto ,  Toru Kaga ,  Shinichiro Kimura ,  Masahiro Moniwa ,  Haruhiko Tanaka ,  Atsushi Hiraiwa ,  Eiji Takeda

IPC分类号： H01L21/336 ,  H01L21/339 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/108 ,  H01L27/11 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L29/785 ,  H01L21/76264 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/10808 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/1108 ,  H01L29/1062 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66954 ,  H01L29/78654 ,  H01L21/76278 ,  Y10S148/014

摘要： A semiconductor device such as FET or charge coupled device, having a channel or a charge coupled portion provided in a thin semiconductor layer which is nearly perpendicular to the substrate and to which the necessary electrode such as the gate electrode and the necessary insulating layer are added can maintain the necessary amount of electric current by securing the height of the semiconductor layer and also can have its plane size reduced minutely. Further, the semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics.

摘要翻译： 一种诸如FET或电荷耦合器件的半导体器件，其具有设置在薄半导体层中的沟道或电荷耦合部分，该半导体层几乎垂直于衬底并且添加诸如栅电极和必需绝缘层的必需电极 可以通过确保半导体层的高度来保持必要的电流量，并且还可以使其平面尺寸微小地减小。 此外，使用上述半导体器件的半导体存储器件适合于高集成度并且具有优异的电特性。

公开(公告)号：US5346834A

公开(公告)日：1994-09-13

申请号：US845063

申请日：1992-03-03

申请人： Dai Hisamoto ,  Toru Kaga ,  Shinichiro Kimura ,  Masahiro Moniwa ,  Haruhiko Tanaka ,  Atsushi Hiraiwa ,  Eiji Takeda

发明人： Dai Hisamoto ,  Toru Kaga ,  Shinichiro Kimura ,  Masahiro Moniwa ,  Haruhiko Tanaka ,  Atsushi Hiraiwa ,  Eiji Takeda

IPC分类号： H01L21/336 ,  H01L21/339 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/108 ,  H01L27/11 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L21/265

CPC分类号： H01L29/785 ,  H01L21/76264 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/10808 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/1108 ,  H01L29/1062 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66954 ,  H01L29/78654 ,  H01L21/76278 ,  Y10S148/014

摘要： An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate. Next a gate electrode is formed on silicon island, followed by forming source and drain regions in the silicon island employing the gate electrode as a mask.

摘要翻译： 提供了一种用于制造绝缘栅场效应晶体管的改进方法。 作为第一步骤，在硅衬底上生长氧化硅膜，并且在其上沉积第一氮化硅膜。 然后使用抗蚀剂图案作为掩模来蚀刻第一硅亚硝酸盐膜，氧化硅膜和硅衬底，以形成包括硅衬底的至少一部分的硅岛。 然后在通过第二步骤暴露的硅衬底的表面上以及在硅岛的表面上生长第二氧化硅膜，并且在其上沉积第二硅亚硝酸盐膜。 然后蚀刻第二硅亚硝酸盐膜以留下沉积在硅岛的侧壁上的第二硅亚硝酸盐膜的一部分。 之后，通过硅衬底的表面的热氧化生长第三氧化硅膜，以将硅岛与硅衬底电隔离。 接下来，在硅岛上形成栅电极，随后在硅岛中形成源极和漏极区域，采用栅电极作为掩模。

公开(公告)号：US5355330A

公开(公告)日：1994-10-11

申请号：US932242

申请日：1992-08-19

申请人： Dai Hisamoto ,  Shoji Shukuri ,  Kazuhiko Sagara ,  Shinichiro Kimura ,  Shinichi Minami ,  Eiji Takeda

发明人： Dai Hisamoto ,  Shoji Shukuri ,  Kazuhiko Sagara ,  Shinichiro Kimura ,  Shinichi Minami ,  Eiji Takeda

IPC分类号： G11C11/40 ,  G11C11/401 ,  H01L27/108 ,  G11C11/24

CPC分类号： G11C11/401 ,  G11C11/40 ,  H01L27/108

摘要： A semiconductor memory device whose data hold condition is not affected due to degradation of transistor characteristics by minimizing leakage charges and the switching transistor size. The semiconductor memory device employs memory cell charge holding electrode that is insulated from the remaining memory cell structure, particularly the switching transistor source drain leakage path. The write element controls the tunneling of charge carriers through such insulator to the charge holding portion or capacitor electrode, for writing data. Particularly, the write element includes a PN junction for various advantages.

摘要翻译： 通过使泄漏电荷和开关晶体管尺寸最小化，由于晶体管特性的劣化，其数据保持条件不受影响的半导体存储器件。 半导体存储器件采用与剩余存储单元结构绝缘的存储单元电荷保持电极，特别是开关晶体管源漏泄漏路径。 写元件控制通过这种绝缘体的电荷载体穿过电荷保持部分或电容器电极，以便写入数据。 特别地，写入元件包括用于各种优点的PN结。

公开(公告)号：US5374576A

公开(公告)日：1994-12-20

申请号：US72482

申请日：1993-06-03

申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

公开(公告)号：US5591998A

公开(公告)日：1997-01-07

申请号：US443106

申请日：1995-05-17

申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

公开(公告)号：US5583358A

公开(公告)日：1996-12-10

申请号：US324352

申请日：1994-10-17

申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

公开(公告)号：US5140389A

公开(公告)日：1992-08-18

申请号：US475148

申请日：1990-02-05

申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

IPC分类号： H01L27/108

CPC分类号： H01L27/10817

摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacitor portions to be arranged very densely and a sufficiently large capacitance to be maintained with very small cell areas. Since the storage capacitor portions are formed even on the bit lines, the bit lines are shielded, so that the capacitance decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacitor portion so that a part thereof is in the form of a wall substantially vertical to the substrate in order to increase the capacitance.

摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储电容器 要非常密集地布置的部分和足够大的电容以保持非常小的电池区域。 由于存储电容器部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的电容减小，因此存储器阵列噪声减小。 也可以设计电荷存储电容器部分，使得其一部分呈基本上垂直于衬底的壁的形式，以增加电容。

公开(公告)号：US06878586B2

公开(公告)日：2005-04-12

申请号：US10458271

申请日：2003-06-11

申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45 ,  H01L21/8242

CPC分类号： H01L27/10817 ,  H01L27/10808 ,  H01L29/41775 ,  H01L29/456

摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

公开(公告)号：US5200635A

公开(公告)日：1993-04-06

申请号：US686757

申请日：1991-04-17

申请人： Toru Kaga ,  Shinichiro Kimura ,  Katsutaka Kimura ,  Yoshinobu Nakagome ,  Digh Hisamoto ,  Yoshifumi Kawamoto ,  Eiji Takeda ,  Shimpei Iijima ,  Tokuo Kure ,  Takashi Nishida

发明人： Toru Kaga ,  Shinichiro Kimura ,  Katsutaka Kimura ,  Yoshinobu Nakagome ,  Digh Hisamoto ,  Yoshifumi Kawamoto ,  Eiji Takeda ,  Shimpei Iijima ,  Tokuo Kure ,  Takashi Nishida

IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L29/41775 ,  H01L27/10817 ,  H01L29/456 ,  H01L2924/0002

摘要： The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.

摘要翻译： 本发明涉及具有低电阻率布线结构的半导体器件。 直接形成在山谷和山谷结构上的布线导致薄的部分，并且在极端情况下是断开的部分。 这增加了山丘和山谷结构上的布线电阻率，降低了连接的可靠性。 在布线是存储器的数据线的情况下，随着有效长度的增加，数据线的电阻和寄生电容更大。 上述问题已经通过包括至少两层导电膜的布线来解决，所述导电膜包括作为下层的第一导电膜和作为上层的第二导电膜，并且第一导电层具有调节或平坦化山丘的表面 和底层材料中的山谷。