公开(公告)号：US5200635A

公开(公告)日：1993-04-06

申请号：US686757

申请日：1991-04-17

申请人： Toru Kaga ,  Shinichiro Kimura ,  Katsutaka Kimura ,  Yoshinobu Nakagome ,  Digh Hisamoto ,  Yoshifumi Kawamoto ,  Eiji Takeda ,  Shimpei Iijima ,  Tokuo Kure ,  Takashi Nishida

发明人： Toru Kaga ,  Shinichiro Kimura ,  Katsutaka Kimura ,  Yoshinobu Nakagome ,  Digh Hisamoto ,  Yoshifumi Kawamoto ,  Eiji Takeda ,  Shimpei Iijima ,  Tokuo Kure ,  Takashi Nishida

IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L29/41775 ,  H01L27/10817 ,  H01L29/456 ,  H01L2924/0002

摘要： The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.

摘要翻译： 本发明涉及具有低电阻率布线结构的半导体器件。 直接形成在山谷和山谷结构上的布线导致薄的部分，并且在极端情况下是断开的部分。 这增加了山丘和山谷结构上的布线电阻率，降低了连接的可靠性。 在布线是存储器的数据线的情况下，随着有效长度的增加，数据线的电阻和寄生电容更大。 上述问题已经通过包括至少两层导电膜的布线来解决，所述导电膜包括作为下层的第一导电膜和作为上层的第二导电膜，并且第一导电层具有调节或平坦化山丘的表面 和底层材料中的山谷。

公开(公告)号：US5532971A

公开(公告)日：1996-07-02

申请号：US354639

申请日：1994-12-13

申请人： Toshihiro Tanaka ,  Masataka Kato ,  Keiichi Yoshida ,  Hitoshi Kume ,  Yoshinobu Nakagome ,  Katsutaka Kimura

发明人： Toshihiro Tanaka ,  Masataka Kato ,  Keiichi Yoshida ,  Hitoshi Kume ,  Yoshinobu Nakagome ,  Katsutaka Kimura

IPC分类号： G11C17/00 ,  G11C8/08 ,  G11C16/06 ,  G11C16/08 ,  G11C16/12 ,  G11C8/00 ,  G11C11/34

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/12

摘要： An arrangement is provided to enhance the speed in the operation of erasing and programming of a nonvolatile semiconductor memory that is driven by a single supply voltage and to reduce the number of transistors making up the subword decoder circuit thereby minimizing the size of the device. For this purpose, in the subword decoder circuits WDi1-WDij that drive the word lines Wi1-Wij, the block selection address lines Bip and Bin generated from the first address line group are used as supply voltages for the inverter circuit that controls the voltage of the word line, and the gate selection address line Gj generated from the second address line group is used a gate input line.

摘要翻译： 提供了一种布置，以提高由单个电源电压驱动的非易失性半导体存储器的擦除和编程操作的速度，并且减少构成子字解码器电路的晶体管的数量，从而使器件的尺寸最小化。 为此，在驱动字线Wi1-Wij的子字解码器电路WDi1-WDij中，将从第一地址线组产生的块选择地址线Bip和Bin用作控制电压的逆变器电路的电源电压 字线和从第二地址线组产生的选通选择地址线Gj用于栅极输入线。

公开(公告)号：US08179733B2

公开(公告)日：2012-05-15

申请号：US13080958

申请日：2011-04-06

申请人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

发明人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

IPC分类号： G11C7/00

CPC分类号： H03L7/107 ,  G11C5/025 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12005 ,  H03L7/0814 ,  H03L7/0898 ,  H03L7/1072 ,  H03L2207/14

摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

摘要翻译： 一种时钟发生电路，用于通过将通过可变延迟电路延迟通过外部端子输入的输入时钟信号与通过相位比较器电路的输入时钟信号相比较而获得的信号进行比较，从而控制延迟时间 的可变延迟电路，其中时钟发生电路和由其形成的时钟信号操作的内部电路形成在公共半导体衬底上，其中元件形成区域 形成时钟的电路与元件形成区电气隔离，其中数字电路依赖元件隔离技术构成在半导体衬底上。 电源通道也与其他数字电路无关地形成。

公开(公告)号：US07602665B2

公开(公告)日：2009-10-13

申请号：US12169253

申请日：2008-07-08

申请人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

发明人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

IPC分类号： G11C5/14

CPC分类号： H03L7/107 ,  G11C5/025 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12005 ,  H03L7/0814 ,  H03L7/0898 ,  H03L7/1072 ,  H03L2207/14

摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

公开(公告)号：US20070177445A1

公开(公告)日：2007-08-02

申请号：US11727429

申请日：2007-03-27

申请人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

发明人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

IPC分类号： G11C5/14

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

摘要翻译： 提供了一种同步DRAM，其包括基于DRAM是否处于掉电模式的电源电路的操作的布置。 在一个实施例中，提供了第一电源电路和第二电源电路，其接收外部提供的电压并输出内部电源电压。 当同步DRAM的半导体器件处于掉电模式时，第一电源电路不工作。 然而，第二电源电路在掉电模式期间连续运行。 在另一种布置中，基于DRAM是否处于断电模式来控制限压器电路的操作。

公开(公告)号：US07199648B2

公开(公告)日：2007-04-03

申请号：US10859141

申请日：2004-06-03

申请人： Masashi Horiguchi ,  Yasushi Kawase ,  Takesada Akiba ,  Yoshinobu Nakagome ,  Kazuhiko Kajigaya

发明人： Masashi Horiguchi ,  Yasushi Kawase ,  Takesada Akiba ,  Yoshinobu Nakagome ,  Kazuhiko Kajigaya

IPC分类号： G05F1/10

CPC分类号： G11C8/08 ,  G11C5/14 ,  G11C5/147 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit is provided having first and second logic circuits coupled to first and second sub-power supply lines, respectively. First and second switching transistors are also provided to connect the first and second sub-power supply lines to a main power supply line. The first and second switching transistors are kept off in an operation stop state of the first and second logic circuits, and are kept on in operable state of the first and second logic circuits.

摘要翻译： 提供半导体集成电路，其具有分别耦合到第一和第二子电源线的第一和第二逻辑电路。 还提供第一和第二开关晶体管以将第一和第二子电源线连接到主电源线。 第一和第二开关晶体管被保持在第一和第二逻辑电路的操作停止状态，并且保持在第一和第二逻辑电路的可操作状态。

公开(公告)号：US20050249017A1

公开(公告)日：2005-11-10

申请号：US11183802

申请日：2005-07-19

申请人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

发明人： Masashi Horiguchi ,  Masayuki Nakamura ,  Sadayuki Ohkuma ,  Kazuhiko Kajigaya ,  Yoshinobu Nakagome

IPC分类号： G11C11/413 ,  G11C5/06 ,  G11C5/14 ,  G11C7/10 ,  G11C8/00 ,  G11C8/12 ,  G11C11/401 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/147 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

公开(公告)号：US20050023615A1

公开(公告)日：2005-02-03

申请号：US10929424

申请日：2004-08-31

申请人： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

发明人： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC分类号： H01L21/8247 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/04 ,  G11C16/28 ,  H01L21/28 ,  H01L21/336 ,  H01L27/01 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L31/036 ,  H01L31/062 ,  H01L31/112 ,  H01L31/113

CPC分类号： B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

摘要： A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

摘要翻译： 一种场效应半导体元件，其具有较少数量的元件和减小的面积，并能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。 栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。 通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。

公开(公告)号：US06594197B2

公开(公告)日：2003-07-15

申请号：US10185044

申请日：2002-07-01

申请人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

发明人： Yuichi Okuda ,  Masaru Kokubo ,  Yoshinobu Nakagome ,  Hideharu Yahata ,  Hiroki Miyashita

IPC分类号： H03K300

CPC分类号： H03L7/107 ,  G11C5/025 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/12 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12005 ,  H03L7/0814 ,  H03L7/0898 ,  H03L7/1072 ,  H03L2207/14

摘要： A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

公开(公告)号：US06519173B2

公开(公告)日：2003-02-11

申请号：US10161634

申请日：2002-06-05

申请人： Seiji Funaba ,  Yoji Nishio ,  Yoshinobu Nakagome

发明人： Seiji Funaba ,  Yoji Nishio ,  Yoshinobu Nakagome

IPC分类号： G11C506

CPC分类号： G11C5/06 ,  G11C5/04 ,  H01L2224/16225 ,  H01L2924/13091 ,  H05K1/0216 ,  H05K1/14 ,  H01L2924/00

摘要： A memory system comprises a controller capable of controlling a memory operation, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips connected to module data wirings and module power wirings respectively. The module data wirings of each memory module are connected in series form through series paths lying within the connectors. Each individual module data wirings do not constitute branch wirings to system data wirings on the system board. Thus, such signal reflection as caused by branching from the data wirings on the system board is not developed. Since the power is supplied in parallel from the system board through parallel paths lying within the connectors, the supply of the power is stabilized.