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    Wafer-level inter-connector formation method
    2.
    发明授权
    Wafer-level inter-connector formation method 失效
    晶圆级互连器形成方法

    公开(公告)号：US06787456B1

    公开(公告)日：2004-09-07

    申请号：US10392084

    申请日：2003-03-20

    申请人： Vaidyanathan Kripesh ,  Mahadevan K Iyer ,  Ranganathan Nagarajan

    发明人： Vaidyanathan Kripesh ,  Mahadevan K Iyer ,  Ranganathan Nagarajan

    IPC分类号： H01L214763

    CPC分类号： H01L21/4853

    摘要： Inter-connectors are typically used for interconnecting electronic components. Interconnections between electronic components are generally classified into at least two broad categories of “relatively permanent” and “readily demountable”. A “readily demountable” connector includes a spring-like contact structure of one electronic component for connecting to a terminal of another electronic component. The spring-like contact structure, also known as an inter-connector, generally requires a certain amount of contact force to effect reliable pressure contact to a terminal of an electronic component. Therefore, the shape and metallurgy of the inter-connector are important factors in determining the effectiveness of the inter-connector for making pressure connection to a terminal of the electronic component. Conventional methods of making such an inter-connector use lithographic and planarisation methods to “make” the inter-connectors in segments. This results in the inter-connector segments having joints therebetween. Metallurgically, the joint stress due to joining a pair of inter-connector segments and stress concentration at the joints due forces applied to the inter-connector can lead to the mechanical failure of the inter-connector in Mathieu. An embodiment of the invention uses lithographic techniques and heat treatment methods for forming a structure channel defining the shape and dimension of an inter-connector. The structure channel is then used to “mold” a reproduction of the inter-connector having a single continuous physical segment.

    摘要翻译： 互连器件通常用于互连电子部件。 电子部件之间的互连通常分为至少两大类“相对永久”和“易拆卸”。 “易拆卸”连接器包括用于连接到另一电子部件的端子的一个电子部件的弹簧状接触结构。 也称为相互连接器的弹簧状接触结构通常需要一定量的接触力来实现与电子部件的端子的可靠的压力接触。 因此，连接器的形状和冶金是确定用于与电子部件的端子进行压力连接的连接器的有效性的重要因素。 制造这种连接器的常规方法使用光刻和平面化方法来“制造”分段中的连接器。 这导致连接件之间具有接头。 在冶金方面，由于连接一对连接器间部分而引起的接头应力和施加在连接器上的接头应力集中会导致Mathieu中连接器的机械故障。 本发明的实施例使用光刻技术和热处理方法来形成限定连接器的形状和尺寸的结构通道。 然后，结构通道用于“模制”具有单个连续物理段的连接器的再现。

    Method of forming through-wafer interconnects for vertical wafer level packaging
    8.
    发明授权
    Method of forming through-wafer interconnects for vertical wafer level packaging 失效
    形成用于垂直晶片级封装的贯穿晶片互连的方法

    公开(公告)号：US07381629B2

    公开(公告)日：2008-06-03

    申请号：US11705480

    申请日：2007-02-12

    申请人： Chirayarikathuveedu Premachandran Sankarapillai ,  Ranganathan Nagarajan ,  Mohanraj Soundarapandian

    发明人： Chirayarikathuveedu Premachandran Sankarapillai ,  Ranganathan Nagarajan ,  Mohanraj Soundarapandian

    IPC分类号： H01L21/46

    CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A substrate having target transfer regions thereon is provided. A sacrificial wafer is coated with a polymer layer with low adhesion to metals. A conductive layer is coated on the polymer layer and covered with a photoresist layer which is patterned to provide openings to the conductive layer. Thin film and passive or active device structures are formed on the conductive layer within the openings. The substrate is bonded to the sacrificial wafer wherein the thin film and passive or active device structures and the photoresist layer provide the bonding and wherein the thin film and passive or active device structures contact the substrate at the target transfer regions. The photoresist is stripped in a high frequency agitation bath wherein the photoresist separates from the sacrificial wafer and wherein the thin film and passive or active device structures separate from the polymer layer to complete transfer bonding.

    摘要翻译： 提供其上具有目标转印区域的基板。 牺牲晶片涂覆有对金属具有低粘附性的聚合物层。 将导电层涂覆在聚合物层上并用被图案化以向导电层提供开口的光致抗蚀剂层覆盖。 在开口内的导电层上形成薄膜和无源或有源器件结构。 衬底被结合到牺牲晶片，其中薄膜和无源或有源器件结构和光致抗蚀剂层提供接合，并且其中薄膜和无源或有源器件结构在目标转移区域接触衬底。 光致抗蚀剂在高频搅拌槽中剥离，其中光致抗蚀剂与牺牲晶片分离，其中薄膜和被动或主动器件结构与聚合物层分离以完成转移键合。

    Fully salicided (FUCA) MOSFET structure
    9.
    发明授权
    Fully salicided (FUCA) MOSFET structure 失效
    完全水化（FUSA）MOSFET结构

    公开(公告)号：US07682914B2

    公开(公告)日：2010-03-23

    申请号：US11981496

    申请日：2007-10-30

    申请人： Patrick Guo Qiang Lo ,  Wei Yip Loh ,  Ranganathan Nagarajan ,  Narayanan Balasubramanian

    发明人： Patrick Guo Qiang Lo ,  Wei Yip Loh ,  Ranganathan Nagarajan ,  Narayanan Balasubramanian

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78621 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66643 ,  H01L29/66772 ,  H01L29/78636

    摘要： A method is described to form a MOSFET with a fully silicided gate electrode and fully silicided, raised S/D elements that are nearly coplanar to allow a wider process margin when forming contacts to silicided regions. An insulator block layer is formed over STI regions and a conformal silicidation stop layer such as Ti/TiN is disposed on the insulator block layer and active region. A polysilicon layer is deposited on the silicidation stop layer and is planarized by a CMP process to form raised S/D elements. An oxide hardmask on the gate electrode is removed to produce a slight recess between the spacers. A silicidation process yields a gate electrode and raised S/D elements comprised of NiSi. Optionally, a recess is formed in the substrate between an insulator block mask and spacer and a Schottky barrier is used instead of a silicidation stop layer to form a Schottky Barrier MOSFET.

    摘要翻译： 描述了一种形成具有完全硅化栅电极和完全硅化的凸起S / D元件的MOSFET，该S / D元件几乎共面以在形成与硅化物区域的接触时允许更宽的工艺裕度。 在STI区域上形成绝缘体阻挡层，并且在绝缘体阻挡层和有源区上设置诸如Ti / TiN的共形硅化停止层。 多晶硅层沉积在硅化终止层上，并通过CMP工艺平坦化以形成凸起的S / D元件。 去除栅电极上的氧化物硬掩模以在间隔件之间产生轻微的凹陷。 硅化工艺产生栅电极和由NiSi组成的升高的S / D元件。 可选地，在绝缘体块掩模和间隔物之间​​的衬底中形成凹部，并且使用肖特基势垒代替硅化阻挡层以形成肖特基势垒MOSFET。

    High aspect ratio trench isolation process for surface micromachined sensors and actuators
    10.
    发明授权
    High aspect ratio trench isolation process for surface micromachined sensors and actuators 失效
    表面微加工传感器和执行器的高纵横比沟槽隔离工艺

    公开(公告)号：US06573154B1

    公开(公告)日：2003-06-03

    申请号：US09696082

    申请日：2000-10-26

    申请人： Uppili Sridhar ,  Ranganathan Nagarajan ,  Yu Bo Miao ,  Yi Su

    发明人： Uppili Sridhar ,  Ranganathan Nagarajan ,  Yu Bo Miao ,  Yi Su

    IPC分类号： H01L2176

    CPC分类号： B81C1/00619

    摘要： A process for fabricating an integrated circuit sensor/actuator is described. High aspect ratio deep silicon beams are formed by a process of deep trench etch and silicon undercut release etch by using oxide spacers to protect the silicon beam sidewalls during release etch. An oxide layer is then formed, followed by deposition of a controlled thickness of polysilicon which is then thermally oxidized. The polysilicon layer inside the trenches gets fully oxidized resulting in void-free trench isolation. This process creates a silicon island or beam on three sides leaving the third side for interfacing with the sensor/actuator beams. The sensor/actuator is formed by a similar process of deep trench etch and release etch process on the same substrate. These suspended beams of the sensors and actuators are bridged with the silicon islands from the fourth side. The above process finally results in suspended silicon beams connected to electrically isolated silicon islands.

    摘要翻译： 描述了一种用于制造集成电路传感器/致动器的工艺。 通过使用氧化物间隔物的深沟槽蚀刻和硅蚀刻蚀刻蚀刻的工艺形成高纵横比深硅光束，以在释放蚀刻期间保护硅束侧壁。 然后形成氧化物层，然后沉积受控厚度的多晶硅，然后热氧化。 沟槽内的多晶硅层被完全氧化，导致无空隙的沟槽隔离。 该过程在三侧产生硅岛或光束，离开第三侧以与传感器/致动器光束接口。 传感器/致动器通过在同一衬底上的深沟槽蚀刻和释放蚀刻工艺的类似工艺形成。 这些传感器和致动器的悬挂梁与第四侧的硅岛桥接。 上述过程最终导致连接到电隔离硅岛的悬浮硅束。