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22 条记录 (耗时 0.038 秒)

    Connector assembly
    1.
    发明申请
    Connector assembly 失效
    连接器组件

    公开(公告)号：US20060240697A1

    公开(公告)日：2006-10-26

    申请号：US11114287

    申请日：2005-04-26

    申请人： Daniel Cronch ,  Alexander Barr ,  Wing Chow ,  Steven Feldman ,  Richard Scherer

    发明人： Daniel Cronch ,  Alexander Barr ,  Wing Chow ,  Steven Feldman ,  Richard Scherer

    IPC分类号： H01R13/15

    CPC分类号： H01R12/79 ,  H01R12/774 ,  H01R12/777

    摘要： A connector assembly includes a frame mounted on a printed circuit substrate having a plurality of contact pads, and a spring member configured for insertion into the frame. The spring member has a flexible circuit supported thereon. The spring member and frame are shaped to exert biasing forces in two non-parallel directions when the spring member is inserted into the frame.

    摘要翻译： 连接器组件包括安装在具有多个接触垫的印刷电路基板上的框架，以及构造成用于插入框架中的弹簧构件。 弹簧构件具有支撑在其上的柔性电路。 当弹簧构件插入框架中时，弹簧构件和框架成形为在两个非平行方向上施加偏压力。

    VIRTUAL DESIGNER
    4.
    发明申请
    VIRTUAL DESIGNER 失效
    虚拟设计师

    公开(公告)号：US20070136031A1

    公开(公告)日：2007-06-14

    申请号：US11567035

    申请日：2006-12-05

    申请人： Steven Feldman ,  Jason Randall ,  Alexander Barr ,  Abhay Joshi

    发明人： Steven Feldman ,  Jason Randall ,  Alexander Barr ,  Abhay Joshi

    IPC分类号： G06F17/50 ,  G06F19/00

    CPC分类号： G06F17/50

    摘要： The present invention includes a method of electronically designing an article, including accessing an electronic article design system, selecting an article type to design, and iteratively configuring a group of characteristics by selecting one or more options for each characteristic and/or iteratively modeling the article performance based on a selection of one or more performance parameters for each performance model. In the iterative configuration and modeling step, the electronic article design system automatically presents the characteristics and the performance models based on the article type selected, dynamically updates the article for each step of the iterative configuration and/or modeled performance, and automatically resolves conflicts between iteratively configured characteristics, between iteratively modeled performances, and across iteratively configured characteristics and modeled performances.

    摘要翻译： 本发明包括一种电子设计物品的方法，包括访问电子物品设计系统，选择物品类型进行设计，并且通过为每个特征选择一个或多个选项和/或对物品进行迭代建模来迭代地配置一组特征 基于为每个性能模型选择一个或多个性能参数的性能。 在迭代配置和建模步骤中，电子文章设计系统根据所选择的文章类型自动呈现特征和性能模型，为迭代配置和/或建模性能的每个步骤动态更新文章，并自动解决 迭代配置的特征，迭代建模的性能之间，以及跨迭代配置的特征和建模性能。

    Graded semiconductor layer
    5.
    发明申请
    Graded semiconductor layer 有权
    分级半导体层

    公开(公告)号：US20060040433A1

    公开(公告)日：2006-02-23

    申请号：US10919952

    申请日：2004-08-17

    申请人： Mariam Sadaka ,  Shawn Thomas ,  Ted White ,  Chun-Li Liu ,  Alexander Barr ,  Bich-Yen Nguyen ,  Voon-Yew Thean

    发明人： Mariam Sadaka ,  Shawn Thomas ,  Ted White ,  Chun-Li Liu ,  Alexander Barr ,  Bich-Yen Nguyen ,  Voon-Yew Thean

    IPC分类号： H01L21/84

    CPC分类号： H01L29/78687 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66742

    摘要： A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.

    摘要翻译： 一种形成半导体器件的方法。 该方法包括形成用于形成应变硅层的模板层。 在一个示例中，形成梯度硅锗层，其中锗在下部处具有较高的浓度，在顶部处的浓度较低。 当进行冷凝处理时，层的顶部的锗扩散到硅锗层的剩余部分。 由于硅锗层在下部具有较高的锗浓度，所以在硅锗层的剩余部分的上部可以减少在冷凝后堆积的锗。

    Method for making a semiconductor structure using silicon germanium
    6.
    发明申请
    Method for making a semiconductor structure using silicon germanium 有权
    使用硅锗制造半导体结构的方法

    公开(公告)号：US20050245092A1

    公开(公告)日：2005-11-03

    申请号：US10836172

    申请日：2004-04-30

    申请人： Marius Orlowski ,  Alexander Barr ,  Mariam Sadaka ,  Ted White

    发明人： Marius Orlowski ,  Alexander Barr ,  Mariam Sadaka ,  Ted White

    IPC分类号： H01L21/31 ,  H01L21/316 ,  H01L21/321 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10

    CPC分类号： H01L29/1054 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/31658 ,  H01L21/32105 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  Y10S438/933

    摘要： A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.

    摘要翻译： 提供了具有硅层的半导体衬底。 在一个实施例中，衬底是具有在硅层下面的氧化物层的绝缘体上硅（SOI）衬底。 在硅层上形成非晶或多晶硅锗层。 或者，将锗注入硅层的顶部以形成非晶硅锗层。 然后氧化硅锗层以将硅锗层转化为二氧化硅层，并将至少一部分硅层转化为富含锗的硅。 然后在使用富含锗的硅形成晶体管之前去除二氧化硅层。 在一个实施例中，使用硅层上方的图案化掩模层和硅锗层选择性地形成富锗富硅。 或者，可以使用隔离区来限定其中形成富锗的硅的衬底的局部区域。

    Semiconductor device structure and method therefor
    10.
    发明申请
    Semiconductor device structure and method therefor 有权
    半导体器件结构及其方法

    公开(公告)号：US20060094169A1

    公开(公告)日：2006-05-04

    申请号：US10977423

    申请日：2004-10-29

    申请人： Ted White ,  Alexander Barr ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean

    发明人： Ted White ,  Alexander Barr ,  Bich-Yen Nguyen ,  Marius Orlowski ,  Mariam Sadaka ,  Voon-Yew Thean

    IPC分类号： H01L21/84 ,  H01L21/00

    CPC分类号： H01L29/78696 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/66772

    摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.

    摘要翻译： 在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。 衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。 底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。 然后在氧掺杂半导体层上外延生长半导体层。 在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。 然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。 不同类型的晶体管形成在不同的结晶取向上。