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公开(公告)号：US5894592A
公开(公告)日：1999-04-13
申请号：US839290
申请日：1997-04-17
CPC分类号： H03C3/0975 , H03C3/0941 , H03C3/0966 , H04B1/005 , H04B1/0057 , H04B1/0092 , H04B1/40
摘要： A wideband phase-lock loop frequency synthesizer (200) used in a radio transceiver capable of being reconfigured to operate in either a transmit, receive, or battery save mode. The wideband phase-lock loop frequency synthesizer (200) includes, a divide-by-two divider (205), quadrature detector (204), offset VCO (209) and offset mixer (207) for generating a quadrature phase modulated signal. Moreover, a programmable filter (211) is used for removing predetermined harmonic components of the offset mixed signal enabling the synthesizer to operate over a wide frequency range.
摘要翻译： 一种用于无线电收发机的宽带锁相环频率合成器（200），能够被重新配置为在发射，接收或电池节省模式下工作。 宽带锁相环频率合成器（200）包括用于产生正交相位调制信号的除以二分频器（205），正交检波器（204），偏移VCO（209）和偏移混频器（207）。 此外，可编程滤波器（211）用于去除偏移混合信号的预定谐波分量，使合成器能够在宽的频率范围内工作。
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公开(公告)号：US5953640A
公开(公告)日：1999-09-14
申请号：US847648
申请日：1997-04-30
CPC分类号： H04B1/403
摘要： A single-chip transceiver integrated circuit (100) has multiple on-chip circuits that implement receiver functions, transmitter functions, and audio processing functions. The IC (100) has interfaces (220, 240, 252, 270, 260, 245, 288, 290) which are situated among the on-chip circuits, and which couple one on-chip circuit to another. At least some of these on-chip interfaces (220, 240, 245, 252, 270) are configurable to couple an off-chip processing circuit to substitute for a corresponding on-chip circuit. In the preferred embodiment, the single-chip transceiver IC (100) supports radio configurations having off-chip versions of corresponding on-chip circuits for performing receiver front-end functions, synthesizer functions, reference oscillator functions, and audio processing functions.
摘要翻译： 单片收发器集成电路（100）具有多个片上电路，其实现接收机功能，发射机功能和音频处理功能。 IC（100）具有位于片上电路之间并且将一个片上电路耦合到另一片上的接口（220,240,252,270,260,245,288,290）。 这些片上接口（220,240,245,252,270）中的至少一些可配置为耦合片外处理电路以替代相应的片上电路。 在优选实施例中，单片收发器IC（100）支持具有用于执行接收机前端功能，合成器功能，参考振荡器功能和音频处理功能的相应片上电路的片外版本的无线电配置。
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公开(公告)号：US07539462B2
公开(公告)日：2009-05-26
申请号：US11199737
申请日：2005-08-09
IPC分类号： H04B1/02
CPC分类号： H04B1/0483 , H03F1/0205 , H03F1/34 , H03F3/24 , H03F2200/294 , H03F2200/372 , H04B1/406 , H04B2001/0433
摘要： A multi-mode transmitter architecture is configurable for multiple modulation modes using either polar or polar-lite modulation. Multiplexed signal paths and reconfigurable components are controlled for performance in GMSK and EDGE burst modes. Polar-lite EDGE modulation is programmed by setting a multiplexer coupling a first amplitude modulated signal path with a frequency modulated signal path input to a dual-mode power amplifier for amplification of the combined EDGE transmission signal. In full-polar EDGE modulation, amplitude modulated signal is multiplexed into a second amplitude modulated signal path for A/D conversion and comparison with a polar feedback signal coupled from the power amplifier output. The resulting comparison is applied to a power control port of the power amplifier to amplitude modulate the EDGE transmission output. Multiplexers are configured to disconnect the amplitude modulated paths when operating in GMSK signaling for both full-polar and polar-lite modulation. Multiplexers selectively couple power feedback into the second amplitude modulated signal path to provide power control and output power ramping for burst transmissions.
摘要翻译： 多模式发射机架构可以使用极性或极性微调制来配置多种调制模式。 控制多路复用信号路径和可重构组件，以实现GMSK和EDGE突发模式的性能。 通过设置将第一幅度调制信号路径与输入到双模功率放大器的频率调制信号路径耦合的多路复用器来编程极性EDGE调制，以放大组合EDGE传输信号。 在全极性EDGE调制中，幅度调制信号被多路复用到第二幅度调制信号路径用于A / D转换，并与从功率放大器输出耦合的极性反馈信号进行比较。 所得到的比较被应用于功率放大器的功率控制端口以幅度调制EDGE传输输出。 多路复用器被配置为在GMSK信号中进行全极性和极坐标调制时断开幅度调制路径。 多路复用器将功率反馈选择性地耦合到第二幅度调制信号路径中，以提供突发传输的功率控制和输出功率斜坡。
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公开(公告)号：US06246213B1
公开(公告)日：2001-06-12
申请号：US09515247
申请日：2000-02-29
IPC分类号： H01M1044
CPC分类号： G06F1/324 , G06F1/24 , G06F1/3203 , G06F1/3287 , H01M10/44 , H02J9/005 , H04W52/029 , Y02D10/126 , Y02D10/171 , Y02D70/00
摘要： A device having battery-save circuitry includes a power-on reset circuit (603), an OR-gate (604) coupled to the power-on reset circuit (603), a current-boost timer circuit (602) coupled to the OR-gate (604), a reference oscillator (403) with a start-up current mode enabled by the current-boost timer circuit (602), and a low current secondary reference oscillator (613). A method of operating the device includes operating the device in a battery-save mode and an active mode. A first clock signal is used as a microprocessor clock signal while operating the device in the battery-save mode, and a second or third clock signal is used as the microprocessor clock signal while operating the device in the active mode.
摘要翻译： 具有电池保存电路的装置包括上电复位电路（603），耦合到上电复位电路（603）的或门（604），耦合到OR的电流升压定时器电路（602） - 门（604），具有由电流升压定时器电路（602）使能的启动电流模式的参考振荡器（403）和低电流次参考振荡器（613）。 操作该设备的方法包括以电池节省模式和活动模式操作该设备。 第一时钟信号用作微处理器时钟信号，同时在电池保存模式下操作器件，并且在处于活动模式下操作器件时，使用第二或第三时钟信号作为微处理器时钟信号。
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公开(公告)号：US5584062A
公开(公告)日：1996-12-10
申请号：US427926
申请日：1995-04-26
申请人： Richard B. Meador , Joseph P. Heck
发明人： Richard B. Meador , Joseph P. Heck
CPC分类号： H03J5/0272 , H03D3/00 , H04B1/16 , H03D7/00
摘要： Receiver section (200) includes a compensation network (202) which compensates for undesired effects caused by synthesized LO (204). Compensation network (202) substantially duplicates the amplitude and phase delay of synthesized LO (204) allowing for a substantially flat demodulated frequency response to be achieved at output (122) which is independent of the bandwidth of synthesized LO (204).
摘要翻译： 接收器部分（200）包括补偿网络（202），其补偿由合成LO（204）引起的不期望的影响。 补偿网络（202）基本上复制合成LO（204）的幅度和相位延迟，允许在独立于合成LO（204）的带宽的输出（122）处实现基本平坦的解调频率响应。
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公开(公告)号：US4385279A
公开(公告)日：1983-05-24
申请号：US289868
申请日：1981-08-04
申请人： Richard B. Meador
发明人： Richard B. Meador
摘要： A helical cavity resonator having a grounded shield, a hollow coil form and associated quarter wavelength wire coil. A non-ferrous conductive slug can be adjusted to variable positions inside the hollow coil form. Placement of the slug in a region proximate to the inside of the wire coil tunes the cavity resonator in a predominately inductive manner. Changing the slug position in the bore so that it is proximate to the shield top and removed from the inside of the wire coil tunes the cavity resonator in a predominately capacitive manner. By utilizing both inductive and capacitive tuning a helical cavity resonator with a wide tuning range is realized while maintaining a simple, inexpensive construction.
摘要翻译： 具有接地屏蔽，中空线圈形式和相关四分之一波长线圈的螺旋空腔谐振器。 有色金属导电块可以调节到空心线圈形式内的可变位置。 芯片在靠近线圈内部的区域中的放置以主要感应的方式调谐空腔谐振器。 改变孔中的块塞位置使其靠近屏蔽顶部并从线圈内部移除，以主要电容的方式调谐空腔谐振器。 通过利用电感和电容调谐，实现具有宽调谐范围的螺旋空腔谐振器，同时保持简单，便宜的结构。
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公开(公告)号：US20100041353A1
公开(公告)日：2010-02-18
申请号：US12191831
申请日：2008-08-14
IPC分类号： H04B17/00
CPC分类号： H04B17/21 , H04B17/101 , H04B17/14
摘要： A technique for calibrating a transceiver of a wireless communication device includes selectively coupling an output node of a transmitter of the transceiver to an input node of a receiver of the transceiver. A calibration signal is provided, from the output node of the transmitter, to the input node of the receiver. The calibration signal is down-converted, with the receiver, to provide a down-converted calibration signal. A discrete Fourier transform is performed on the down-converted calibration signal. Finally, one or more correction factors are determined based on an analysis of the discrete Fourier transform of the down-converted calibration signal. At least one of the correction factors is utilized to facilitate substantial cancellation of a direct current offset associated with the transceiver.
摘要翻译： 用于校准无线通信设备的收发器的技术包括将收发器的发射机的输出节点选择性地耦合到收发器的接收机的输入节点。 从发射机的输出节点向接收机的输入节点提供校准信号。 校准信号与接收器进行下变频，以提供下变频校准信号。 对下变频校准信号进行离散傅里叶变换。 最后，基于对下变频校准信号的离散傅里叶变换的分析来确定一个或多个校正因子。 使用校正因子中的至少一个来促进与收发器相关联的直流偏移的实质性消除。
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公开(公告)号：US06747987B1
公开(公告)日：2004-06-08
申请号：US09514804
申请日：2000-02-29
IPC分类号： H04J316
CPC分类号： H03C3/095 , H03C3/0933 , H03J1/0008 , H03L7/0893 , H03L7/099 , H03L7/10 , H03L7/1976
摘要： A transmitter (100) includes a fractional N synthesizer, a baseband digital modulation stage coupled to the fractional N synthesizer in a first modulation mode, and a baseband I/Q modulation stage also coupled to the fractional N synthesizer and reusing the fractional N synthesizer in a second modulation mode. A method (300) of operating a transmitter includes transmitting a first signal from a transmitter using the fractional N synthesizer and the baseband digital modulation stage to modulate the first signal according to a first wireless protocol. The method (300) also includes transmitting a second signal from the transmitter using the baseband I/Q modulation stage and the fractional N synthesizer to modulate the second signal according to a second wireless protocol.
摘要翻译： 发射机（100）包括分数N个合成器，以第一调制模式耦合到分数N个合成器的基带数字调制级，以及还耦合到分数N个合成器的基带I / Q调制级，并且重新使用分数N个合成器 第二调制模式。 操作发射机的方法（300）包括使用分数N个合成器和基带数字调制级从发射机发射第一信号，以根据第一无线协议对第一信号进行调制。 方法（300）还包括使用基带I / Q调制级和小数N合成器从发射机发送第二信号，以根据第二无线协议来调制第二信号。
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公开(公告)号：US06564039B1
公开(公告)日：2003-05-13
申请号：US09515728
申请日：2000-02-29
IPC分类号： H04B140
CPC分类号： H04B1/406 , H03L7/23 , H04B2001/0491
摘要： A frequency generation circuit includes an oscillator (403), a comparator (413) coupled to the oscillator, a first divider (407) coupled to the comparator, a PLL (400) coupled to the first divider, a second divider (422) coupled to the PLL, a first multiplexor (409) coupled to the second divider, a third divider (408) coupled to the comparator and the first multiplexor, a second multiplexor (410) coupled to the comparator and the reference clock PLL, a fourth divider (411) coupled to the second multiplexor, a fifth divider (412) coupled to the comparator, and a seventh divider (450) coupled to the comparator. A method of operating a transceiver includes using the frequency generation circuit to provide a first clock signal, a second clock signal, a first reference frequency, and a second reference frequency for a first component, a second component, a third component, and a fourth component, respectively, of the transceiver.
摘要翻译： 频率发生电路包括振荡器（403），耦合到振荡器的比较器（413），耦合到比较器的第一分频器（407），耦合到第一分频器的PLL（400），耦合到第一分频器 耦合到所述PLL，耦合到所述第二分频器的第一多路复用器（409），耦合到所述比较器和所述第一多路复用器的第三分频器（408），耦合到所述比较器和所述参考时钟PLL的第二多路复用器（410） （411），耦合到所述第二多路复用器，耦合到所述比较器的第五分频器（412）和耦合到所述比较器的第七分频器（450）。 操作收发器的方法包括使用频率产生电路为第一组件，第二组件，第三组件和第四组件提供第一时钟信号，第二时钟信号，第一参考频率和第二参考频率 分别为收发器。
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10.发明授权公开(公告)号：US08548400B2
公开(公告)日：2013-10-01
申请号：US11445981
申请日：2006-05-31
IPC分类号： H04B1/04
CPC分类号： H03G3/3047
摘要： Systems and techniques are described for applying a polar bias modulation having a phase component and an amplitude component to a signal amplified by a power amplifier. The power amplifier (PA) has a plurality of amplifier gain stages and is configured to amplify an input to create an amplifier output signal. The input to the power amplitude is phase modulated based upon the phase component of the polar bias modulation, but need not be amplitude modulated. Amplitude modulation is provided by logic that includes a detector configured to receive an indication of the amplifier output as a feedback signal, a control module configured to generate a control signal based upon both the feedback signal and the amplitude component of the polar bias modulation, and a bias circuit configured to adjust a bias signal associated with at least one of the plurality of amplifier gain stages in response to the control signal. Such a modulation scheme may be readily applied in enhanced data rate for global service mode (GSM) evolution (EDGE) applications, as well as in other environments that make use of polar modulation.
摘要翻译： 描述了将系统和技术应用于具有相位分量和幅度分量的极性偏置调制到由功率放大器放大的信号。 功率放大器（PA）具有多个放大器增益级，并且被配置为放大输入以产生放大器输出信号。 基于极化偏置调制的相位分量，对功率振幅的输入进行相位调制，但不需要进行幅度调制。 幅度调制由逻辑提供，逻辑包括被配置为接收放大器输出的指示作为反馈信号的检测器，控制模块被配置为基于反馈信号和极偏调制的幅度分量来产生控制信号，以及 偏置电路，被配置为响应于所述控制信号调整与所述多个放大器增益级中的至少一个相关联的偏置信号。 这种调制方案可以容易地应用于全球服务模式（GSM）演进（EDGE）应用的增强数据速率以及利用极化调制的其它环境中。
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