公开(公告)号：US06512701B1

公开(公告)日：2003-01-28

申请号：US09886861

申请日：2001-06-21

申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Yider Wu

发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Yider Wu

IPC分类号： G11C1604

CPC分类号： G11C16/16 ,  G11C16/0475 ,  G11C16/0491

摘要： A system and methodology is provided for verifying erasure of one or more dual bit virtual ground memory cells in a memory device, such as a flash memory. Each of the dual bits have a first or normal bit and a second or complimentary bit associated with the first or normal bit. The system and methodology include verifying and erasure of both a normal bit and a complimentary bit of the cell. The erasure includes applying a set of erase pulses to the normal bit and complimentary bit in a single dual bit cell. The set of erase pulses is comprised of a two sided erase pulse to both sides of the bits in the cell or transistor junction followed by a first single sided erase pulse to one side and a second single sided erase pulse to the other side of transistor junction.

摘要翻译： 提供了用于验证擦除存储器设备（例如闪存）中的一个或多个双位虚拟接地存储器单元的系统和方法。 每个双位具有与第一或正常位相关联的第一或正常位和第二或补充位。 系统和方法包括验证和擦除单元的正常位和互补位。 擦除包括将一组擦除脉冲施加到单个双位单元中的正常位和补充位。 该组擦除脉冲由单元或晶体管结中的位的两侧的双侧擦除脉冲组成，之后是一侧的第一单侧擦除脉冲和到晶体管结的另一侧的第二单侧擦除脉冲 。

公开(公告)号：US06707078B1

公开(公告)日：2004-03-16

申请号：US10230729

申请日：2002-08-29

申请人： Hidehiko Shiraiwa ,  Yider Wu ,  Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Darlene G. Hamilton

发明人： Hidehiko Shiraiwa ,  Yider Wu ,  Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Darlene G. Hamilton

IPC分类号： H01L2968

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L27/115

摘要： One aspect of the present invention relates to a SONOS type non-volatile semiconductor memory device having improved erase speed, the device containing bitlines extending in a first direction; wordlines extending in a second direction, the wordlines comprising functioning wordlines and at least one dummy wordline, wherein the dummy wordline is positioned near at least one of a bitline contact and an edge of the core region, and the dummy wordline is treated so as not to cycle between on and off states. Another aspect of the present invention relates to a method of making a SONOS type non-volatile semiconductor memory device having improved erase speed, involving forming a plurality of bitlines extending in a first direction in the core region; forming a plurality of functioning wordlines extending in a second direction in the core region; forming at least one dummy wordline between the functioning wordlines and the periphery region or between the functioning wordlines and a bitline contact and treating the device so that the dummy wordline does not cycle between on and off states.

摘要翻译： 本发明的一个方面涉及一种具有改进的擦除速度的SONOS型非易失性半导体存储器件，该器件含有沿第一方向延伸的位线; 所述字线在第二方向上延伸，所述字线包括功能字线和至少一个伪字线，其中所述伪字线位于所述芯区域的位线接触和边缘中的至少一个附近，并且所述伪字线被处理为不 在开关状态之间循环。 本发明的另一方面涉及一种制造具有改进的擦除速度的SONOS型非易失性半导体存储器件的方法，包括形成在芯区域中沿第一方向延伸的多个位线; 形成在所述芯区域中沿第二方向延伸的多个功能字线; 在功能字线和外围区域之间或在功能字线和位线接触之间形成至少一个伪字线，并对器件进行处理，使得伪字线不会在导通和关断状态之间循环。

公开(公告)号：US06344994B1

公开(公告)日：2002-02-05

申请号：US09795849

申请日：2001-02-28

申请人： Darlene G. Hamilton ,  Yider Wu ,  Michael Han

发明人： Darlene G. Hamilton ,  Yider Wu ,  Michael Han

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C5/063 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3454

摘要： Dummy wordlines are provided between gaps of blocks of memory cells to compensate for higher charge loss at higher stress temperatures exhibited at edge wordlines of blocks of memory cells having large gaps. The dummy wordlines minimize the gap between the blocks. The dummy wordlines can be positioned between the blocks. Alternatively, the wordline width for the last block or sector wordline can be changed or different nitride used with less conductance in high temperatures. The dummy wordlines are typically ignored in normal operations on the memory.

摘要翻译： 在存储单元块的间隙之间提供虚拟字线以补偿在具有大间隙的存储器单元的块的边缘字线处表现的较高应力温度下的较高电荷损失。 虚拟字线最小化块之间的差距。 虚拟字线可以位于块之间。 或者，可以改变最后一个块或扇区字线的字线宽度，或者在高温下以较小的电导率使用不同的氮化物。 通常在内存的正常操作中忽略伪字线。

公开(公告)号：US10297607B2

公开(公告)日：2019-05-21

申请号：US13615723

申请日：2012-09-14

申请人： Takao Akaogi ,  Yider Wu ,  Yi-Hsiu Chen

发明人： Takao Akaogi ,  Yider Wu ,  Yi-Hsiu Chen

IPC分类号： H01L27/11565 ,  H01L21/762 ,  H01L27/11568 ,  H01L21/8234

摘要： A non-volatile memory having discrete isolation structures and SONOS (Silicon Oxide Nitride Oxide Silicon) memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.

公开(公告)号：US08012825B2

公开(公告)日：2011-09-06

申请号：US12350298

申请日：2009-01-08

申请人： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

发明人： Yider Wu ,  Yung-Chung Lee ,  Yi-Hsiu Chen

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.

摘要翻译： 在制造双注入NOR NOR闪存结构的方法中，执行磷离子注入工艺，使得在两个栅极结构之间的半导体衬底中形成P掺杂漏极区，以与高掺杂漏极（HDD ）区域和轻掺杂漏极（LDD）区域。 因此，解决了HDD区域和LDD区域之间的连接处的电连接，并且解决了存储器中的载流子迁移率，同时解决了LDD区域的短沟道效应和穿通问题。

公开(公告)号：US20100227447A1

公开(公告)日：2010-09-09

申请号：US12399124

申请日：2009-03-06

申请人： Hung-Wei Chen ,  Yider Wu

发明人： Hung-Wei Chen ,  Yider Wu

IPC分类号： H01L21/8234

CPC分类号： H01L27/11519 ,  H01L29/40114

摘要： A flash memory device manufacturing process includes the steps of providing a semiconductor substrate; forming two gate structures on the substrate; performing an ion implantation process to form two first source regions in the substrate at two lateral outer sides of the two gate structures; performing a further ion implantation process to form a first drain region in the substrate between the two gate structures; performing a pocket implantation process between the gate structures to form two doped regions in the substrate at two opposite sides of the first drain region; forming two facing L-shaped spacer walls between the two gate structures above the first drain region; performing an ion implantation process to form a second drain region beneath the first drain region, both of which having a steep junction profile compared to the first source regions; and forming a barrier plug above the first drain region.

摘要翻译： 闪存器件制造方法包括以下步骤：提供半导体衬底; 在基板上形成两个栅极结构; 执行离子注入工艺以在两个栅极结构的两个侧向外侧处在衬底中形成两个第一源极区域; 执行另外的离子注入工艺以在所述两个栅极结构之间的所述衬底中形成第一漏极区; 在所述栅极结构之间执行凹穴注入工艺，以在所述衬底中在所述第一漏极区的两个相对侧形成两个掺杂区域; 在所述第一漏极区域之上的所述两个栅极结构之间形成两个面对的L形间隔壁; 执行离子注入工艺以在所述第一漏极区域下方形成第二漏极区域，所述第二漏极区域与所述第一源极区域相比具有陡峭的接合轮廓; 以及在所述第一漏极区域上方形成阻挡塞。

公开(公告)号：US20100197108A1

公开(公告)日：2010-08-05

申请号：US12761460

申请日：2010-04-16

申请人： Yider Wu

发明人： Yider Wu

IPC分类号： H01L21/28 ,  H01L21/762

CPC分类号： H01L29/78 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile semiconductor manufacturing method comprises the steps of making element isolation/insulation films that partitions element-forming regions in a semiconductor substrate; stacking a floating gate on the semiconductor substrate via a first gate insulating film; stacking a second gate insulating film formed on the floating gate, and stacking a control gate formed on the floating gate via the second gate insulating film, and self-aligning source and drain diffusion area with the control gate. In the process of stacking a floating gate by partially etching a field oxide film in a select gate area, followed by floating gate formed in a element-forming region and select gate region, and followed by a chemical mechanical polish(CMP) process, both floating gate and select gate is hereby formed simultaneously. Thereby, when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density.

摘要翻译： 非易失性半导体制造方法包括以下步骤：制造在半导体衬底中分隔元件形成区域的元件隔离/绝缘膜; 通过第一栅极绝缘膜在半导体衬底上堆叠浮置栅极; 堆叠形成在浮置栅极上的第二栅极绝缘膜，并且通过第二栅极绝缘膜堆叠形成在浮置栅极上的控制栅极以及与控制栅极的自对准源极和漏极扩散区域。 在通过在选择栅极区域中局部蚀刻场氧化物膜的同时堆叠浮栅的过程中，随后是形成在元件形成区域中的浮栅并选择栅极区域，然后进行化学机械抛光（CMP）工艺， 浮动门和选择门同时形成。 因此，当存储单元小型化时，本发明允许该过程简单并减少缺陷密度。

公开(公告)号：US20070026675A1

公开(公告)日：2007-02-01

申请号：US11193409

申请日：2005-08-01

申请人： Unsoon Kim ,  Angela Hui ,  Yider Wu ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita

发明人： Unsoon Kim ,  Angela Hui ,  Yider Wu ,  Kuo-Tung Chang ,  Hiroyuki Kinoshita

IPC分类号： H01L21/302

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11531

摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.

摘要翻译： 提供了一种用于形成存储器件的方法。 在衬底上形成氮化物层。 蚀刻氮化物层和衬底以形成沟槽。 在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。 沟槽填充有氧化物材料。 从存储器件剥离氮化物层，在沟槽上方形成台面。

公开(公告)号：US06509232B1

公开(公告)日：2003-01-21

申请号：US09969573

申请日：2001-10-01

申请人： Unsoon Kim ,  Mark S. Chang ,  Yider Wu ,  Chi Chang ,  Angela Hui ,  Yu Sun

发明人： Unsoon Kim ,  Mark S. Chang ,  Yider Wu ,  Chi Chang ,  Angela Hui ,  Yu Sun

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

摘要： STI (shallow trench isolation) structures are formed for a flash memory device fabricated within an semiconductor substrate comprised of a core area having an array of core flash memory cells fabricated therein and comprised of a periphery area having logic circuitry fabricated therein. A first set of STI (shallow trench isolation) openings within the core area are etched through the semiconductor substrate, and a second set of STI (shallow trench isolation) openings within the periphery area are etched through the semiconductor substrate. A core active device area of the semiconductor substrate within the core area is surrounded by the first set of STI openings, and a periphery active device area of the semiconductor substrate within the periphery area is surrounded by the second set of STI openings. Dielectric liners are formed at sidewalls of the first and second sets of STI openings with reaction of the semiconductor substrate at the sidewalls of the STI openings such that top corners of the semiconductor substrate of the core and periphery active device areas adjacent the STI openings are rounded. A trench dielectric material is deposited to fill the STI openings. In addition, the top corners of the periphery active device area are exposed by etching portions of the sidewalls of the second set of STI structures in a dip-off etch. The exposed top corners of the periphery active device area are further rounded after additional thermal oxidation of the exposed top corners of the periphery active device area. The rounded corners of the core and periphery active device areas result in minimized leakage current through a flash memory cell fabricated within the core active device area and through a MOSFET fabricated within the periphery active device area.

摘要翻译： 形成STI（浅沟槽隔离）结构，用于制造在半导体衬底内的闪存器件，该半导体衬底由具有在其中制造的核心闪存单元阵列的核心区域组成，并由其中制造的逻辑电路的外围区域组成。 核心区域内的第一组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底，并且外围区域内的第二组STI（浅沟槽隔离）开口被蚀刻穿过半导体衬底。 核心区域内的半导体衬底的核心有源器件区域由第一组STI开口包围，并且周边区域内的半导体衬底的外围有源器件区域被第二组STI开口包围。 电介质衬垫通过半导体衬底在STI开口的侧壁处的反应而形成在第一和第二组STI开口的侧壁处，使得芯部的半导体衬底和邻近STI开口的周边有源器件区域的顶角是圆形的 。 沉积沟槽电介质材料以填充STI开口。 此外，通过在浸渍蚀刻中蚀刻第二组STI结构的侧壁的部分来暴露外围有源器件区域的顶角。 外围有源器件区域的暴露的顶角在外围有源器件区域的暴露顶角的额外的热氧化之后被进一步倒圆。 核心和外围有源器件区域的圆角导致通过在核心有源器件区域内制造的闪存单元和通过在外围有源器件区域内制造的MOSFET的最小化的漏电流。

公开(公告)号：US06468865B1

公开(公告)日：2002-10-22

申请号：US09723653

申请日：2000-11-28

申请人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

发明人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; forming a bitline isolation over the buried bitlines in the core region; and forming gates in the core region and the periphery region. Another aspect of the present invention relates to increasing the thickness of the gate dielectric in at least a portion of the periphery region simultaneously while forming the bitline isolation.

摘要翻译： 本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 去除位于芯区域中的掩埋位线之上的电荷捕获电介质的至少一部分; 在核心区域的掩埋位线上形成位线隔离; 并且在芯区域和周边区域中形成栅极。 本发明的另一方面涉及在形成位线隔离的同时在周边区域的至少一部分中增加栅极电介质的厚度。