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    Dummy wordline for erase and bitline leakage
    1.
    发明授权
    Dummy wordline for erase and bitline leakage 有权
    用于擦除和位线泄漏的虚拟字线

    公开(公告)号：US06707078B1

    公开(公告)日：2004-03-16

    申请号：US10230729

    申请日：2002-08-29

    申请人： Hidehiko Shiraiwa ,  Yider Wu ,  Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Darlene G. Hamilton

    发明人： Hidehiko Shiraiwa ,  Yider Wu ,  Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Darlene G. Hamilton

    IPC分类号： H01L2968

    CPC分类号： H01L27/11568 ,  G11C16/0466 ,  H01L27/115

    摘要： One aspect of the present invention relates to a SONOS type non-volatile semiconductor memory device having improved erase speed, the device containing bitlines extending in a first direction; wordlines extending in a second direction, the wordlines comprising functioning wordlines and at least one dummy wordline, wherein the dummy wordline is positioned near at least one of a bitline contact and an edge of the core region, and the dummy wordline is treated so as not to cycle between on and off states. Another aspect of the present invention relates to a method of making a SONOS type non-volatile semiconductor memory device having improved erase speed, involving forming a plurality of bitlines extending in a first direction in the core region; forming a plurality of functioning wordlines extending in a second direction in the core region; forming at least one dummy wordline between the functioning wordlines and the periphery region or between the functioning wordlines and a bitline contact and treating the device so that the dummy wordline does not cycle between on and off states.

    摘要翻译： 本发明的一个方面涉及一种具有改进的擦除速度的SONOS型非易失性半导体存储器件，该器件含有沿第一方向延伸的位线; 所述字线在第二方向上延伸，所述字线包括功能字线和至少一个伪字线，其中所述伪字线位于所述芯区域的位线接触和边缘中的至少一个附近，并且所述伪字线被处理为不 在开关状态之间循环。 本发明的另一方面涉及一种制造具有改进的擦除速度的SONOS型非易失性半导体存储器件的方法，包括形成在芯区域中沿第一方向延伸的多个位线; 形成在所述芯区域中沿第二方向延伸的多个功能字线; 在功能字线和外围区域之间或在功能字线和位线接触之间形成至少一个伪字线，并对器件进行处理，使得伪字线不会在导通和关断状态之间循环。

    Source drain implant during ONO formation for improved isolation of SONOS devices
    2.
    发明授权
    Source drain implant during ONO formation for improved isolation of SONOS devices 有权
    在ONO形成期间的源极漏极注入，以改善SONOS器件的隔离

    公开(公告)号：US06436768B1

    公开(公告)日：2002-08-20

    申请号：US09893279

    申请日：2001-06-27

    申请人： Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Emmanuil Manos Lingunis ,  Yider Wu ,  Tazrien Kamal ,  Yi He ,  Edward Hsia ,  Hidehiko Shiraiwa

    发明人： Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Emmanuil Manos Lingunis ,  Yider Wu ,  Tazrien Kamal ,  Yi He ,  Edward Hsia ,  Hidehiko Shiraiwa

    IPC分类号： H01L21336

    CPC分类号： H01L21/2652 ,  H01L21/2658 ,  H01L27/11568 ,  H01L29/66833

    摘要： One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.

    摘要翻译： 本发明的一个方面涉及一种形成SONOS型非易失性半导体存储器件的方法，包括在半导体衬底上形成电荷俘获电介质的第一层; 在所述半导体衬底上的所述电荷俘获电介质的所述第一层上形成所述电荷俘获电介质的第二层; 可选地至少部分地在所述半导体衬底上的所述电荷俘获电介质的所述第二层上形成所述电荷俘获电介质的第三层; 任选地去除电荷俘获电介质的第三层; 在电荷俘获电介质上形成源极/漏极掩模; 将源极/漏极注入物通过电荷俘获电介质注入到半导体衬底中; 任选地去除电荷俘获电介质的第三层; 以及在半导体衬底上的电荷俘获电介质的第二层上形成电荷俘获电介质的第三层之一，在半导体衬底上的电荷俘获电介质的第二层上重整第三层电荷俘获电介质，或 在电荷俘获电介质的第三层上形成附加材料。

    Method of simultaneous formation of bitline isolation and periphery oxide
    3.
    发明授权
    Method of simultaneous formation of bitline isolation and periphery oxide 有权
    同时形成位线隔离和周边氧化物的方法

    公开(公告)号：US06468865B1

    公开(公告)日：2002-10-22

    申请号：US09723653

    申请日：2000-11-28

    申请人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

    发明人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; forming a bitline isolation over the buried bitlines in the core region; and forming gates in the core region and the periphery region. Another aspect of the present invention relates to increasing the thickness of the gate dielectric in at least a portion of the periphery region simultaneously while forming the bitline isolation.

    摘要翻译： 本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 去除位于芯区域中的掩埋位线之上的电荷捕获电介质的至少一部分; 在核心区域的掩埋位线上形成位线隔离; 并且在芯区域和周边区域中形成栅极。 本发明的另一方面涉及在形成位线隔离的同时在周边区域的至少一部分中增加栅极电介质的厚度。

    Hard mask process for memory device without bitline shorts
    4.
    发明授权
    Hard mask process for memory device without bitline shorts 有权
    内存设备的硬掩模处理，无位线短路

    公开(公告)号：US06706595B2

    公开(公告)日：2004-03-16

    申请号：US10100485

    申请日：2002-03-14

    申请人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Yider Wu ,  Emmanuil Lingunis ,  Tazrien Kamal

    发明人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Yider Wu ,  Emmanuil Lingunis ,  Tazrien Kamal

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. The hard mask is of a material formulated for removal without damaging the charge-trapping dielectric layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A salicide is grown without short-circuiting the first and second bitlines.

    摘要翻译： 用于MirrorBit（闪存）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质层。 植入第一和第二位线，并存放字线层。 硬掩模层沉积在字线层上。 硬掩模是配制用于去除而不损坏电荷捕获介电层的材料。 光刻胶沉积在字线层上并用于形成硬掩模。 去除光致抗蚀剂。 使用硬掩模处理字线层以形成字线，并且去除硬掩模。 生长自杀剂不会使第一和第二位线短路。

    Alignment marks with salicided spacers between bitlines for alignment signal improvement
    7.
    发明授权
    Alignment marks with salicided spacers between bitlines for alignment signal improvement 有权
    对准标记与位线之间的水平间隔物，用于对准信号改善

    公开(公告)号：US07098546B1

    公开(公告)日：2006-08-29

    申请号：US10869286

    申请日：2004-06-16

    申请人： Emmanuil H. Lingunis ,  Jean Yee-Mei Yang ,  Hidehiko Shiraiwa

    发明人： Emmanuil H. Lingunis ,  Jean Yee-Mei Yang ,  Hidehiko Shiraiwa

    IPC分类号： H01L23/544 ,  H01L21/76

    CPC分类号： H01L27/115 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L27/11568 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： The present invention pertains to utilizing a salicide in establishing alignment marks in semiconductor fabrication. A metal layer is formed over exposed portions of a silicon substrate as well as oxide areas formed over bitlines buried within the substrate. The metal layer is treated to react with the exposed portions of the silicon substrate to form salicided areas. The metal layer does not, however, react with the oxide areas. As such, salicided areas are formed adjacent to the oxide areas to provide an enhanced optical contrast when light is shined there-upon. In this manner, the alignment marks can be more readily “seen”. The enhanced optical contrast thus allows the marks to continue to be seen as scaling occurs.

    摘要翻译： 本发明涉及在半导体制造中利用硅化物建立对准标记。 在硅衬底的暴露部分上形成金属层，以及形成在衬底内的位线之间形成的氧化物区域。 处理金属层与硅衬底的暴露部分反应以形成咸水区域。 然而，金属层不与氧化物区域反应。 因此，在氧化物区域附近形成有咸水区域，以在其上照射光时提供增强的光学对比度。 以这种方式，对准标记可以更容易地“看到”。 因此，增强的光学对比度允许标记继续被看作是发生缩放。

    Method for forming wordlines having irregular spacing in a memory array
    8.
    发明授权
    Method for forming wordlines having irregular spacing in a memory array 有权
    用于形成在存储器阵列中具有不规则间隔的字线的方法

    公开(公告)号：US07052961B1

    公开(公告)日：2006-05-30

    申请号：US11003574

    申请日：2004-12-03

    申请人： Hidehiko Shiraiwa ,  Jean Yee-Mei Yang ,  Jaeyong Park ,  Cyrus E. Tabery

    发明人： Hidehiko Shiraiwa ,  Jean Yee-Mei Yang ,  Jaeyong Park ,  Cyrus E. Tabery

    IPC分类号： H01L21/336 ,  H01L21/302

    CPC分类号： H01L27/11568 ,  H01L21/0337 ,  H01L27/11521

    摘要： According to one exemplary embodiment, a method of fabricating memory array includes forming a number of hard mask lines and at least one dummy hard mask line on a layer of polysilicon, where the at least one dummy hard mask line is situated in a bitline contact region of the memory array. The method further includes removing the at least one dummy hard mask line. According to this embodiment, the method further includes forming a number of wordlines, where each of the wordlines is situated under one of the hard mask lines, and where the bitline contact region causes an irregularity in spacing of the wordlines. Two of the wordlines are situated adjacent to the bitline contact region such that the spacing between the two wordlines is substantially equal to a width of the bit line contact region.

    摘要翻译： 根据一个示例性实施例，制造存储器阵列的方法包括在多晶硅层上形成多个硬掩模线和至少一个虚拟硬掩模线，其中至少一个虚拟硬掩模线位于位线接触区域 的存储器阵列。 该方法还包括移除至少一个虚拟硬掩模线。 根据该实施例，该方法还包括形成多个字线，其中每个字线位于硬掩模线之一之下，并且其中位线接触区域引起字线间隔的不规则。 两个字线位于与位线接触区域相邻的位置，使得两个字线之间的间隔基本上等于位线接触区域的宽度。

    Alignment system for planar charge trapping dielectric memory cell lithography
    9.
    发明授权
    Alignment system for planar charge trapping dielectric memory cell lithography 有权
    平面电荷俘获介质存储单元光刻对准系统

    公开(公告)号：US06667212B1

    公开(公告)日：2003-12-23

    申请号：US10394565

    申请日：2003-03-21

    申请人： Hidehiko Shiraiwa ,  Jean Yee-Mei Yang ,  Kouros Ghandehari

    发明人： Hidehiko Shiraiwa ,  Jean Yee-Mei Yang ,  Kouros Ghandehari

    IPC分类号： H01L218242

    CPC分类号： H01L27/11568 ,  G03F7/70425 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L27/105 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a charge trapping dielectric memory cell array comprises exposing a first photoresist to a first illumination pattern from a first mask to pattern bit line regions in a core region of the wafer and to pattern alignment mark regions. The alignment mark regions may be in a scribe lane region of the wafer. An impurity is implanted into the wafer within the bit line regions and the alignment mark regions and an oxide is grown on the surface of the wafer in the scribe lane region to produce oxide protrusions within the alignment mark regions. A second photoresist is exposed to a second illumination pattern from a second mask to pattern word line regions within the core region of the wafer and utilizing surface height variations of the oxide protrusions to detect alignment between the second mask and the first mask.

    摘要翻译： 一种制造电荷俘获介质存储单元阵列的方法包括将第一光致抗蚀剂从第一掩模暴露于第一照明图案，以在晶片的芯区域中图案化位线区域，并且形成对准标记区域。 对准标记区域可以在晶片的划线路区域中。 在位线区域和对准标记区域内的晶片中注入杂质，在划线路区域的晶片表面生长氧化物，在对准标记区域内产生氧化物突起。 第二光致抗蚀剂从第二掩模暴露于第二照明图案，以在晶片的芯区域内图案化字线区域，并且利用氧化物突起的表面高度变化来检测第二掩模和第一掩模之间的对准。