公开(公告)号：US06235163B1

公开(公告)日：2001-05-22

申请号：US09350556

申请日：1999-07-09

申请人： Darryl Angelo ,  Arvind Sundarrajan ,  Peijun Ding ,  James H. Tsung ,  Ilyoung R. Hong ,  Barry Chin

发明人： Darryl Angelo ,  Arvind Sundarrajan ,  Peijun Ding ,  James H. Tsung ,  Ilyoung R. Hong ,  Barry Chin

IPC分类号： C23C1434

CPC分类号： H01J37/321 ,  H01J37/32724 ,  H01J37/34

摘要： An improved system for performing plasma enhanced PVD of copper, aluminum, tungsten or other metallic material is disclosed. The system has markedly improved performance in the critical area of unwanted in-film particle deposits. The improved performance is provided by lowering the operating temperature of the RF coil used in the plasma enhanced PVD system and by carefully smoothing the outer surface of the RF coil. High conductivity material in the coil supports, increased contact area between the coil supports and the RF coil, and the use of active cooling of the coil further enhance the performance of the system.

摘要翻译： 公开了一种用于执行铜，铝，钨或其它金属材料的等离子体增强PVD的改进的系统。 该系统在不需要的膜内颗粒沉积的关键区域显着改善了性能。 通过降低等离子体增强PVD系统中使用的RF线圈的工作温度以及仔细地平滑RF线圈的外表面来提供改进的性能。 线圈支架中的高导电性材料，线圈支架与RF线圈之间的接触面积增加，线圈主动冷却的使用进一步增强了系统的性能。

公开(公告)号：US06458251B1

公开(公告)日：2002-10-01

申请号：US09440679

申请日：1999-11-16

申请人： Arvind Sundarrajan ,  Darryl Angelo ,  Peijun Ding ,  Barry Chin ,  Imran Hasim

发明人： Arvind Sundarrajan ,  Darryl Angelo ,  Peijun Ding ,  Barry Chin ,  Imran Hasim

IPC分类号： C23C1432

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/3492 ,  C23C14/358 ,  H01J37/32082 ,  H01J37/3402 ,  H01J2237/3327 ,  H01L21/2855 ,  H01L21/76873 ,  H01L21/76877

摘要： A multi-step process for the deposition of a material into high aspect ratio features on a substrate surface is provided. The process involves depositing a material on the substrate at a first pressure for a first period of time and then depositing the material on the substrate at a second pressure for a second period of time. Modulation of the pressure influences the ionization and trajectory of the particles, which are ionized in a plasma environment. The method of the invention in one aspect allows for optimum deposition at the bottom of a high aspect ratio feature during a high pressure step and increased deposition on the sidewalls of the feature during at least a low pressure step.

摘要翻译： 提供了用于将材料沉积到衬底表面上的高纵横比特征的多步骤过程。 该方法包括在第一压力下在第一时间段内将材料沉积在衬底上，然后在第二压力下将材料沉积在衬底上持续第二段时间。 压力的调制影响在等离子体环境中离子化的颗粒的电离和轨迹。 在一个方面，本发明的方法允许在高压步骤期间在高纵横比特征的底部进行最佳沉积，并且在至少低压步骤期间在特征的侧壁上增加沉积。

公开(公告)号：US20070178682A1

公开(公告)日：2007-08-02

申请号：US11733671

申请日：2007-04-10

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/20

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using an ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) of the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.

摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括 步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被侵蚀或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。 在施加阻挡层时，使用标准溅射技术或使用离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）组合， 受离子影响的表面不会以对器件性能或寿命有害的量溅射。 随后，使用离子沉积溅射在增加的衬底偏置电压下施加阻挡材料的第二部分，这导致阻挡层材料的第一部分的再溅射（雕刻），同时能够进行更多的各向异性沉积新沉积的材料。 应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。

公开(公告)号：US20050020080A1

公开(公告)日：2005-01-27

申请号：US10922052

申请日：2004-08-18

申请人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

发明人： Tony Chiang ,  Gongda Yao ,  Peijun Ding ,  Fusen Chen ,  Barry Chin ,  Gene Kohara ,  Zheng Xu ,  Hong Zhang

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76843 ,  C23C14/046 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, said method comprising the steps of: a) applying a first portion of a sculptured layer with sufficiently low substrate bias that a surface onto which said sculptured layer is applied is not eroded away or contaminated in an amount which is harmful to said semiconductor device performance or longevity; and b) applying a subsequent portion of said sculptured layer with sufficiently high substrate bias to sculpture a shape from said the first portion, while depositing additional layer material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces and is especially helpful when the conductive layer is copper. In the application of a barrier layer, a first portion of barrier layer material is deposited on the substrate surface using standard sputtering techniques or using all ion deposition plasma, but in combination with sufficiently low substrate bias voltage (including at no applied substrate voltage) that the surfaces impacted by ions are not sputtered in an amount which is harmful to device performance or longevity. Subsequently, a second portion of barrier material is applied using ion deposition sputtering at increased substrate bias voltage which causes resputtering (sculpturing) or the first portion of barrier layer material, while enabling a more anisotropic deposition of newly depositing material. A conductive material, and particularly a copper seed layer applied to the feature may be accomplished using the same sculpturing technique as that described above with reference to the barrier layer.

摘要翻译： 我们公开了使用离子沉积溅射在半导体特征表面上施加雕刻层的材料的方法，其中施加有雕刻层的表面被保护以通过冲击沉积层的离子来抵抗侵蚀和污染，所述方法包括 步骤：a）以足够低的衬底偏压施加雕刻层的第一部分，使得施加所述雕刻层的表面不会以对所述半导体器件的性能或寿命有害的量被侵蚀或污染; 以及b）将所述雕刻层的后续部分施加足够高的衬底偏压，以从所述第一部分雕刻形状，同时沉积附加层材料。 该方法特别适用于在半导体特征表面上雕刻阻挡层，润湿层和导电层，并且当导电层是铜时尤其有用。 在施加阻挡层时，使用标准溅射技术或使用所有离子沉积等离子体将阻挡层材料的第一部分沉积在衬底表面上，但是与足够低的衬底偏置电压（包括没有施加的衬底电压）相结合， 受离子影响的表面不会以对器件性能或寿命有害的量溅射。 随后，使用离子沉积溅射以增加的衬底偏置电压施加阻挡材料的第二部分，其引起再溅射（雕刻）或阻挡层材料的第一部分，同时能够进行更多的各向异性沉积新沉积材料。 应用于特征的导电材料，特别是铜种子层可以使用与上述参考阻挡层所述相同的雕刻技术来实现。

公开(公告)号：US06313033B1

公开(公告)日：2001-11-06

申请号：US09362923

申请日：1999-07-27

申请人： Tony Chiang ,  Bingxi Sun ,  Suraj Rengarajan ,  Peijun Ding ,  Barry Chin

发明人： Tony Chiang ,  Bingxi Sun ,  Suraj Rengarajan ,  Peijun Ding ,  Barry Chin

IPC分类号： H01L2144

CPC分类号： H01L27/1087 ,  H01L21/2855 ,  H01L21/76843 ,  H01L28/40 ,  H01L28/56 ,  H01L28/75

摘要： The invention provides a method for forming a microelectronic device comprising: forming a first electrode; depositing an adhesion layer over the first electrode utilizing high density plasma physical vapor deposition, wherein the adhesion layer comprises a material selected from Ta, TaNx, W, WNx, Ta/TaNx, W/WNx, and combinations thereof, depositing a dielectric layer over the adhesion layer; and forming a second electrode over the dielectric layer. The invention also provides a microelectronic device comprising: a first electrode; a second electrode; a dielectric layer disposed between the first and second electrodes; and an adhesion layer disposed between the first electrode and the dielectric layer, wherein the adhesion layer comprises a material selected from Ta, TaNx, W, WNx, Ta/TaNx, W/WNx, and combinations thereof.

摘要翻译： 本发明提供一种形成微电子器件的方法，包括：形成第一电极; 使用高密度等离子体物理气相沉积在第一电极上沉积粘合层，其中粘合层包括选自Ta，TaNx，W，WNx，Ta / TaNx，W / WNx的材料及其组合，将介电层沉积在 粘合层; 以及在所述电介质层上形成第二电极。 本发明还提供了一种微电子器件，包括：第一电极; 第二电极; 设置在所述第一和第二电极之间的电介质层; 以及设置在第一电极和电介质层之间的粘合层，其中粘合层包括选自Ta，TaNx，W，WNx，Ta / TaNx，W / WNx的材料及其组合。

公开(公告)号：US06066892A

公开(公告)日：2000-05-23

申请号：US79107

申请日：1998-05-14

申请人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

发明人： Peijun Ding ,  Tony Chiang ,  Imran Hashim ,  Bingxi Sun ,  Barry Chin

IPC分类号： H01L21/28 ,  C23C14/02 ,  C23C14/16 ,  C23C16/02 ,  C23C16/06 ,  H01L21/203 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L29/45

CPC分类号： H01L21/76843 ,  C23C14/024 ,  C23C14/025 ,  C23C14/16 ,  C23C14/165 ,  C23C16/0281 ,  C23C16/06 ,  H01L21/28556 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L21/2855 ,  H01L2924/0002

摘要： A copper metallization structure in which a layer of a copper alloy, such as Cu--Mg or Cu--Al is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferred examples of the alloying elements and their atomic alloying percentage include magnesium between 0.05 and 6% and aluminum between 0.05 and 0.3%. Further examples include boron, tantalum, tellurium, and titanium. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.

摘要翻译： 在铜合金层上沉积铜基金属化结构，其中在氧化硅基介电层和基本上纯的铜层上沉积诸如Cu-Mg或Cu-Al的铜合金层。 铜合金层用作种子或润湿层，用于随后用基本上纯的铜填充通孔和沟槽。 合金元素的优选实例及其原子合金化百分比包括0.05至6％的镁和0.05-0.3％的铝。 其他实例包括硼，钽，碲和钛。 优选地，铜合金在溅射过程中冷沉积，但是在纯铜层沉积期间或之后在单独的退火步骤中，温度升高到足够高以使铜合金的合金元素迁移到 电介质层，并形成阻挡铜，以扩散到介电层中并穿过介电层。 该屏障还促进了合金层对电介质层的粘附，从而形成了用于随后的铜全填充技术的优异的润湿和种子层。 可以使用PVD，CVD或电/无电镀来完成合金衬里特征的填充。

公开(公告)号：US6037257A

公开(公告)日：2000-03-14

申请号：US853191

申请日：1997-05-08

申请人： Tony Chiang ,  Peijun Ding ,  Barry Chin ,  Imran Hashim ,  Bingxi Sun

发明人： Tony Chiang ,  Peijun Ding ,  Barry Chin ,  Imran Hashim ,  Bingxi Sun

IPC分类号： C23C14/02 ,  C23C14/16 ,  C23C16/02 ,  C23C16/06 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76834 ,  C23C14/024 ,  C23C14/025 ,  C23C14/16 ,  C23C14/165 ,  C23C16/0281 ,  C23C16/06 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53233 ,  H01L23/53238 ,  H01L21/2855 ,  H01L2924/0002

摘要： Copper and a small amount of an alloying metal such as magnesium or aluminum are cosputtered onto a substrate having oxide on at least a portion of its surface. Either the wafer is held at an elevated temperature during deposition or the sputtered film is annealed without the wafer being exposed to ambient. Due to the high temperature, the alloying metal diffuses to the surface. If a surface is exposed to a low partial pressure of oxygen or contacts silicon dioxide, the magnesium or aluminum forms a thin stable oxide. The alloying metal oxide encapsulates the copper layer to provide a barrier against copper migration, to form an adhesion layer over silicon dioxide, and to act as a seed layer for the later growth of copper, for example, by electroplating.

摘要翻译： 将铜和少量合金化金属如镁或铝分散在其表面的至少一部分上具有氧化物的衬底上。 在沉积期间晶片保持在升高的温度下，或者溅射膜被退火而晶片不暴露于环境中。 由于高温，合金金属扩散到表面。 如果表面暴露于低的氧分压或接触二氧化硅，则镁或铝形成薄的稳定的氧化物。 合金化金属氧化物封装铜层以提供阻挡铜迁移的屏障，以形成二氧化硅以上的粘合层，并且作为例如通过电镀的铜的后续生长的种子层。

公开(公告)号：US06881673B2

公开(公告)日：2005-04-19

申请号：US10421174

申请日：2003-04-22

申请人： Peijun Ding ,  Imran Hashim ,  Barry Chin ,  Bingxi Sun

发明人： Peijun Ding ,  Imran Hashim ,  Barry Chin ,  Bingxi Sun

IPC分类号： C23C14/06 ,  C23C14/16 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76876 ,  C23C14/0641 ,  C23C14/165 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76882

摘要： A method and apparatus for metallization process sequences are provided for forming reliable interconnects including lines, vias and contacts. An initial barrier layer, such as Ta or TaN, is first formed on a patterned substrate followed by seed layer formed using high density plasma PVD techniques. The structure is then filled using either 1) electroplating, 2) PVD reflow, 3) CVD followed by PVD reflow, or 4) CVD.

摘要翻译： 提供用于金属化处理序列的方法和装置，用于形成包括线，通孔和触点的可靠的互连。 首先在图案化衬底上形成初始阻挡层，例如Ta或TaN，接着使用高密度等离子体PVD技术形成晶种层。 然后使用1）电镀，2）PVD回流，3）CVD，然后PVD回流或4）CVD来填充该结构。

公开(公告)号：US06790776B2

公开(公告)日：2004-09-14

申请号：US10016255

申请日：2001-12-10

申请人： Peijun Ding ,  Tony Chiang ,  Tse-Yong Yao ,  Barry Chin

发明人： Peijun Ding ,  Tony Chiang ,  Tse-Yong Yao ,  Barry Chin

IPC分类号： C23C1434

CPC分类号： H01L21/76846 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877

摘要： The invention generally provides a method for preparing a surface for electrochemical deposition comprising forming a high conductance barrier layer on the surface and depositing a seed layer over the high conductance barrier layer. Another aspect of the invention provides a method for filling a structure on a substrate, comprising depositing a high conductance barrier layer on one or more surfaces of the structure, depositing a seed layer over the barrier layer, and electrochemically depositing a metal to fill the structure.

摘要翻译： 本发明通常提供了一种用于制备用于电化学沉积的表面的方法，其包括在表面上形成高导电阻挡层并在高导电阻挡层上沉积种子层。 本发明的另一方面提供一种用于在衬底上填充结构的方法，包括在所述结构的一个或多个表面上沉积高电导阻挡层，在所述阻挡层上沉积晶种层，以及电化学沉积金属以填充所述结构 。

公开(公告)号：US06436267B1

公开(公告)日：2002-08-20

申请号：US09650108

申请日：2000-08-29

申请人： Daniel A. Carl ,  Barry Chin ,  Liang Chen ,  Robin Cheung ,  Peijun Ding ,  Yezdi Dordi ,  Imran Hashim ,  Peter Hey ,  Ashok K. Sinha

发明人： Daniel A. Carl ,  Barry Chin ,  Liang Chen ,  Robin Cheung ,  Peijun Ding ,  Yezdi Dordi ,  Imran Hashim ,  Peter Hey ,  Ashok K. Sinha

IPC分类号： C23C2802

CPC分类号： H01L21/2885 ,  H01L21/76877

摘要： One aspect of the invention provides a consistent metal electroplating technique to form void-less metal interconnects in sub-micron high aspect ratio features on semiconductor substrates. One embodiment of the invention provides a method for filling sub-micron features on a substrate, comprising reactive precleaning the substrate, depositing a barrier layer on the substrate using high density plasma physical vapor deposition; depositing a seed layer over the barrier layer using high density plasma physical vapor deposition; and electro-chemically depositing a metal using a highly resistive electrolyte and applying a first current density during a first deposition period followed by a second current density during a second period.

摘要翻译： 本发明的一个方面提供一致的金属电镀技术，以在半导体衬底上形成亚微米高纵横比特征的无空隙金属互连。 本发明的一个实施方案提供了一种用于在基底上填充亚微米特征的方法，包括反应性预清洗基底，使用高密度等离子体物理气相沉积在基底上沉积阻挡层; 使用高密度等离子体物理气相沉积在阻挡层上沉积种子层; 以及使用高电阻电解质电化学沉积金属，并且在第一周期期间在第一沉积期间施加第一电流密度，然后施加第二电流密度。