-
1.发明授权Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit 有权用于在集成电路中提供频率合成和相位对准的方法和装置公开(公告)号：US07499513B1
公开(公告)日：2009-03-03
申请号：US11049329
申请日：2005-02-02
申请人： David E. Tetzlaff , F. Erich Goetting , Steven P. Young , Marwan M. Hassoun , Moises E. Robinson
发明人： David E. Tetzlaff , F. Erich Goetting , Steven P. Young , Marwan M. Hassoun , Moises E. Robinson
CPC分类号： G06F1/10 , H03L7/07 , H03L7/0891 , H03L7/095 , H03L7/183
摘要： According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.
摘要翻译： 根据特定示例性实施例，集成电路包括一个或多个串行数据发送器。 每个这样的数据发射器被布置成在集成电路的相应数据输出端口上发送数据，其中用于至少一个数据发射器的相应数据输出端口专用于发送用于对相应目标电路计时的周期性数据。 在涉及反馈的其他具体实施例中，在可编程逻辑器件（PLD）的功能块中实现了锁相环（PLL）信号控制和/或延迟锁定环（DLL）信号控制。 PLD响应于源时钟并且包括可配置逻辑阵列，其包括可配置逻辑块和可配置路由块，并且用于至少一个数据发射器的相应数据输出端口提供相应的目标时钟。
-
公开(公告)号：US07408380B1
公开(公告)日：2008-08-05
申请号：US11435427
申请日：2006-05-16
IPC分类号： H03K19/003
CPC分类号： H03K19/00392 , H03K19/17736 , H03K19/17744 , H03K19/17764
摘要： A method and apparatus to provide various mechanisms to improve yield of an integrated circuit (IC) employing serial input/output (I/O) communication devices. A single error correction model provides one spare transceiver per group of primary transceivers, whereby reconfiguration of the IC isolates the defective transceiver and configures the replacement transceiver for operation in its place. A multiple error correction model is also provided, whereby multiple replacement transceivers may be configured to replace multiple defective transceivers. The replacement mechanism may occur during various phases of the IC, such as during wafer testing, final testing, or post-deployment testing.
摘要翻译： 提供采用串行输入/输出（I / O）通信设备的集成电路（IC）的收益率的各种机制的方法和装置。 单个错误校正模型每组主收发器提供一个备用收发器，由此IC的重新配置将有缺陷的收发器隔离，并配置替换收发器以便在其位置进行操作。 还提供了多重纠错模型，由此可以将多个替换收发器配置成替换多个有缺陷的收发器。 替换机制可能发生在IC的各个阶段，如晶圆测试，最终测试或部署后测试。
-
公开(公告)号：US07315220B1
公开(公告)日：2008-01-01
申请号：US11340998
申请日：2006-01-27
IPC分类号： H03B5/20
CPC分类号： H03L7/0995 , H03B5/1212 , H03B5/1221 , H03B5/1228 , H03K3/354 , H03K3/356113 , H03L2207/06
摘要： A voltage controlled oscillator (VCO) having a single stage ring-oscillator having both coarse and fine control of the frequency of oscillation is described. In an embodiment the VCO may include a first n-channel latch having a first output and a second output; a first P-channel transistor coupled between a voltage supply and a first VCO output, where a gate of the first P-channel transistor is coupled to the first output of the first n-channel latch; a first programmable resistor circuit coupled between the first VCO output and the first output of the first n-channel latch; and a second n-channel latch coupled to the first VCO output.
摘要翻译： 描述具有振荡频率的粗略和精细控制的具有单级环形振荡器的压控振荡器（VCO）。 在一个实施例中，VCO可以包括具有第一输出和第二输出的第一n沟道锁存器; 耦合在电压源和第一VCO输出端之间的第一P沟道晶体管，其中第一P沟道晶体管的栅极耦合到第一n沟道锁存器的第一输出; 耦合在所述第一VCO输出和所述第一n沟道锁存器的所述第一输出端之间的第一可编程电阻器电路; 以及耦合到第一VCO输出的第二n沟道锁存器。
-
4.发明授权公开(公告)号：US07307460B2
公开(公告)日：2007-12-11
申请号：US11299974
申请日：2005-12-12
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03H11/483 , H03L7/093
摘要： A method and apparatus for capacitance multiplication using two charge pumps. A first charge pump (206) provides a current signal (I216) that is first conducted by a resistor (310) of an RC network and then split into three current paths prior to being conducted by a capacitor of the RC network. A first current path provides current to the capacitor (306) of the RC network from node (320). A second current path multiplies the current conducted by capacitor (306) by a first current multiplication factor. A third current path provides current to a second charge pump, which multiplies the current from the first charge pump by a second current multiplication factor that has a fractional value with an inverse magnitude sign relative to the first current multiplication factor. The combination of the second and third current paths effectively multiplies the capacitance magnitude of capacitor (306).
摘要翻译： 一种使用两个电荷泵进行电容倍增的方法和装置。 第一电荷泵（206）提供首先由RC网络的电阻器（310）传导的电流信号（I T2 216），然后在由电容器传导之前被分成三个电流路径 的RC网络。 第一电流路径从节点（320）向RC网络的电容器（306）提供电流。 第二电流路径将由电容器（306）传导的电流乘以第一电流倍增因子。 第三电流路径向第二电荷泵提供电流，其将来自第一电荷泵的电流乘以具有相对于第一当前倍增因子具有相反幅度符号的分数值的第二电流倍增因子。 第二和第三电流路径的组合有效地乘以电容器的电容量（306）。
-
公开(公告)号：US06809676B1
公开(公告)日：2004-10-26
申请号：US10224977
申请日：2002-08-20
IPC分类号： H03M160
CPC分类号： H03M1/60
摘要： A VCO (110) can be configured to convert an analog input signal (105) to a digital output signal (125). In accordance with the inventive arrangements, the VCO can convert the analog input signal to at least one intermediate signal (130) having a frequency dependent on the analog input signal. A frequency detector (115) can be configured to determine a frequency of at least one intermediate signal. Subsequently, a mapping circuit (120) can be configured to map the determined frequency of the at least one intermediate signal to an output value representing the digital output signal (125).
摘要翻译： VCO（110）可以被配置为将模拟输入信号（105）转换成数字输出信号（125）。 根据本发明的结构，VCO可以将模拟输入信号转换成具有取决于模拟输入信号的频率的至少一个中间信号（130）。 频率检测器（115）可被配置为确定至少一个中间信号的频率。 随后，映射电路（120）可以被配置为将所确定的至少一个中间信号的频率映射到表示数字输出信号（125）的输出值。
-
公开(公告)号：US06624668B1
公开(公告)日：2003-09-23
申请号：US10005736
申请日：2001-11-06
IPC分类号： H02M1100
CPC分类号： H03L7/18 , H03L7/087 , H03L7/0898 , H03L7/0995 , H03L2207/04 , H04L7/0008 , H04L7/02
摘要： Electronic devices are typically coupled together to operate as systems that require the communication of data between two or more devices. Many of these devices includes a communications circuit, such as receiver, transmitter, or transceiver for this purpose. A typical component in these communication circuits is the phase-lock loop, a circuit that in receiver circuits determines the timing of pulses in a received data signal and in transmitter circuits clocks the data out at a predetermined rate. One problem with phase-lock loops and thus the receiver and transmitter circuits that incorporate them is that they are generally tuned, or tailored, to operate at a certain frequency. This means that one cannot generally use a receiver or transmitter circuit having phase-lock loops tuned for one frequency to communicate at another frequency. The inability to communicate at other frequencies limits the usefulness of not only the receiver and transmitter circuits but also their electronic devices. Accordingly, the present inventors devised a digitally programmable phase-lock loop which operates at a frequency selected from a set of two of more frequencies. One such phase-lock loop includes a charge pump, a loop filter, and a voltage-controlled oscillator, all of which are programmable to control the operating frequency of the phase-lock loop and thus devices, such as receivers, transmitters, and transceivers incorporating it. Moreover, the programmability of these three components enables the exemplary embodiment to maintains a constant damping factor and a constant ratio of input frequency to loop bandwidth for each frequency setting, thereby promoting loop stability and rapid settling at each selected frequency.
-
7.发明授权Ring oscillators with improved signal-path matching for high-speed data communications 有权环形振荡器具有改进的信号路径匹配，用于高速数据通信公开(公告)号：US06501339B1
公开(公告)日：2002-12-31
申请号：US09927146
申请日：2001-08-10
IPC分类号： H03B524
CPC分类号： H03L7/0995 , H03K3/0315 , H03L7/087 , H03L7/0891 , H03L7/18
摘要： Electronic devices are typically coupled together to operate as systems that require the communication of data from one device to another. Many such devices include a ring oscillator, a circuit that generates one or more oscillating signals using a series of interconnected delay circuits. One problem with conventional ring oscillators concerns differences in the signal paths between the delay circuits. Accordingly, the present inventors devised several oscillators having unique layouts, which reduce differences in the signal paths between delay circuits. One exemplary oscillator includes a sequence of delay circuits having input-output connections between at least two pairs of non-adjacent delay circuits. Another exemplary oscillator provides two groups of delay circuits with a bus between the two groups, intercoupling the circuits. And, another exemplary oscillator arranges three or more delay circuits to form a closed loop. Applications for these oscillators include not only receivers, transmitters, and transceivers, but also programmable integrated circuits, electronic devices, and systems.
摘要翻译： 电子设备通常耦合在一起以作为需要从一个设备到另一个设备的数据通信的系统进行操作。 许多这样的设备包括环形振荡器，使用一系列互连的延迟电路产生一个或多个振荡信号的电路。 常规环形振荡器的一个问题涉及延迟电路之间的信号路径的差异。 因此，本发明人设计了具有独特布局的几个振荡器，其减小延迟电路之间的信号路径的差异。 一个示例性振荡器包括在至少两对非相邻延迟电路之间具有输入 - 输出连接的延迟电路序列。 另一个示例性振荡器提供两组延迟电路，其中两组之间的总线相互耦合。 并且，另一示例性振荡器布置三个或更多个延迟电路以形成闭环。 这些振荡器的应用不仅包括接收器，发射器和收发器，还包括可编程集成电路，电子设备和系统。
-
公开(公告)号：US07224760B1
公开(公告)日：2007-05-29
申请号：US10421512
申请日：2003-04-22
IPC分类号： H03D3/24
CPC分类号： H04L7/0331 , H03D13/003 , H03L7/087 , H03L7/0896 , H03L7/091 , H03L7/10
摘要： A high-speed, wide bandwidth data detection circuit includes a phase detection module, a data detection module, a loop filter, and a voltage controlled oscillator. The phase detection module is operably coupled to produce a controlled current based on a current mode mathematical manipulation of differences between an incoming data stream and a recovered clock. The phase detection module performs the current mode mathematical manipulations and produces the controlled current in the current domain. The data detection module is operably coupled to produce the detected data based on the incoming data stream and the recovered clock. The loop filter is operably coupled to convert the controlled current into a controlled voltage. The voltage controlled oscillator is operably coupled to convert the control voltage into the recovered clock.
摘要翻译： 高速，宽带宽数据检测电路包括相位检测模块，数据检测模块，环路滤波器和压控振荡器。 相位检测模块可操作地耦合以基于对输入数据流和恢复的时钟之间的差异的当前模式数学操作产生受控电流。 相位检测模块执行当前模式的数学操作并产生当前域中的受控电流。 数据检测模块可操作地耦合以基于输入数据流和恢复的时钟产生检测到的数据。 环路滤波器可操作地耦合以将受控电流转换成受控电压。 压控振荡器可操作地耦合以将控制电压转换成恢复的时钟。
-
公开(公告)号：US06650720B1
公开(公告)日：2003-11-18
申请号：US09218382
申请日：1998-12-22
IPC分类号： H03D324
摘要： A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a high impedance output, a small transconductance value and can provide variable gain control. A coarse loop of the PLL allows for frequency acquisition of an internal oscillator.
摘要翻译： 高速数据通信系统包括从通信数据恢复数据和时钟信号的接收机。 接收器电路具有双锁相环（PLL）电路。 PLL的精细环路包括提供差分模拟电压输出的相位检测器。 跨导电路将差分模拟电压输出转换为低电流模拟输出。 跨导电路具有高阻抗输出，小跨导值，并可提供可变增益控制。 PLL的粗略回路允许对内部振荡器进行频率采集。
-
10.发明授权公开(公告)号：US06356160B1
公开(公告)日：2002-03-12
申请号：US09347256
申请日：1999-07-02
申请人： Moises E. Robinson , Bernard L. Grung , Yiqin Chen
发明人： Moises E. Robinson , Bernard L. Grung , Yiqin Chen
IPC分类号： H03L707
摘要： A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a variable gain which is controlled by an automatic gain adjust circuit. A coarse loop of the PLL allows for fast frequency acquisition of an internal oscillator.
摘要翻译： 高速数据通信系统包括从通信数据恢复数据和时钟信号的接收机。 接收器电路具有双锁相环（PLL）电路。 PLL的精细环路包括提供差分模拟电压输出的相位检测器。 跨导电路将差分模拟电压输出转换为低电流模拟输出。 跨导电路具有由自动增益调节电路控制的可变增益。 PLL的粗略回路允许快速采集内部振荡器。
-
-
-
-
-
-
-
-
-
搜索结果
22 条记录 (耗时 0.029 秒)
