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1.发明授权Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit 有权用于在集成电路中提供频率合成和相位对准的方法和装置公开(公告)号：US07499513B1
公开(公告)日：2009-03-03
申请号：US11049329
申请日：2005-02-02
申请人： David E. Tetzlaff , F. Erich Goetting , Steven P. Young , Marwan M. Hassoun , Moises E. Robinson
发明人： David E. Tetzlaff , F. Erich Goetting , Steven P. Young , Marwan M. Hassoun , Moises E. Robinson
CPC分类号： G06F1/10 , H03L7/07 , H03L7/0891 , H03L7/095 , H03L7/183
摘要： According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.
摘要翻译： 根据特定示例性实施例，集成电路包括一个或多个串行数据发送器。 每个这样的数据发射器被布置成在集成电路的相应数据输出端口上发送数据，其中用于至少一个数据发射器的相应数据输出端口专用于发送用于对相应目标电路计时的周期性数据。 在涉及反馈的其他具体实施例中，在可编程逻辑器件（PLD）的功能块中实现了锁相环（PLL）信号控制和/或延迟锁定环（DLL）信号控制。 PLD响应于源时钟并且包括可配置逻辑阵列，其包括可配置逻辑块和可配置路由块，并且用于至少一个数据发射器的相应数据输出端口提供相应的目标时钟。
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公开(公告)号：US07408380B1
公开(公告)日：2008-08-05
申请号：US11435427
申请日：2006-05-16
IPC分类号： H03K19/003
CPC分类号： H03K19/00392 , H03K19/17736 , H03K19/17744 , H03K19/17764
摘要： A method and apparatus to provide various mechanisms to improve yield of an integrated circuit (IC) employing serial input/output (I/O) communication devices. A single error correction model provides one spare transceiver per group of primary transceivers, whereby reconfiguration of the IC isolates the defective transceiver and configures the replacement transceiver for operation in its place. A multiple error correction model is also provided, whereby multiple replacement transceivers may be configured to replace multiple defective transceivers. The replacement mechanism may occur during various phases of the IC, such as during wafer testing, final testing, or post-deployment testing.
摘要翻译： 提供采用串行输入/输出（I / O）通信设备的集成电路（IC）的收益率的各种机制的方法和装置。 单个错误校正模型每组主收发器提供一个备用收发器，由此IC的重新配置将有缺陷的收发器隔离，并配置替换收发器以便在其位置进行操作。 还提供了多重纠错模型，由此可以将多个替换收发器配置成替换多个有缺陷的收发器。 替换机制可能发生在IC的各个阶段，如晶圆测试，最终测试或部署后测试。
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3.发明授权Method and apparatus for dynamic port provisioning within a programmable logic device 有权用于可编程逻辑器件内的动态端口配置的方法和装置公开(公告)号：US07598768B1
公开(公告)日：2009-10-06
申请号：US11198576
申请日：2005-08-05
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G05B19/054 , H03K19/177 , H03K19/17744 , H04L69/12 , H04L69/32
摘要： A method and apparatus to allow dynamic port provisioning of communication ports within a Programmable Logic Device (PLD). The dynamic port provisioning combines configuration of serial Input/Output (I/O) devices with simultaneous reconfiguration of a portion of programmable logic resources within the PLD and processor functions to implement a particular communication protocol. The dynamic port provisioning is facilitated for a single channel, without affecting the dynamic port provisioning of other communication channels operating within the PLD.
摘要翻译： 允许在可编程逻辑器件（PLD）内的通信端口的动态端口供应的方法和装置。 动态端口配置将串行输入/输出（I / O）设备的配置与PLD中的一部分可编程逻辑资源同时重新配置，并实现特定的通信协议。 为单个通道提供动态端口配置，而不影响在PLD内运行的其他通信通道的动态端口配置。
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公开(公告)号：US07599431B1
公开(公告)日：2009-10-06
申请号：US10997159
申请日：2004-11-24
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H04L25/03038 , H04L25/03057 , H04L25/03343
摘要： A communication system includes a transmitter, a communication channel, and a receiver. The transmitter includes a pre-emphasis module, a summing module, a line driver, and a decision feedback pre-emphasis (DFP) module to produce a pre-emphasized serial stream of data based on a communications channel response and an inter-symbol interference level. The receiver includes a linear equalizer, a summing module, a decision module, and a decision feedback equalization (DFE) module. The linear equalizer produces an equalized serial stream of data. The summing module sums at least one data element of the equalized serial stream of data with DFE data elements to produce equalized data elements. The decision module interprets the equalized data elements to produce interpreted data elements to DFE module, which produces the DFE data elements from the interpreted data elements.
摘要翻译： 通信系统包括发射机，通信信道和接收机。 发射机包括预加重模块，求和模块，线路驱动器和决策反馈预加重（DFP）模块，以基于通信信道响应和符号间干扰产生预先强调的串行数据流 水平。 接收机包括线性均衡器，求和模块，决策模块和判决反馈均衡（DFE）模块。 线性均衡器产生均衡的串行数据流。 求和模块将均衡的串行数据流中的至少一个数据元素与DFE数据元素相加以产生均衡的数据元素。 决策模块解释均衡的数据元素以产生解释的数据元素到DFE模块，其从解释的数据元素产生DFE数据元素。
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5.发明授权Method of adaptive equalization for high-speed NRZ and multi-level signal data communications 有权高速NRZ和多级信号数据通信的自适应均衡方法公开(公告)号：US07426235B1
公开(公告)日：2008-09-16
申请号：US10965938
申请日：2004-10-15
IPC分类号： H04B1/38
CPC分类号： H04L25/03885 , H04L25/03343 , H04L2025/03802
摘要： Circuitry for equalizing a high data rate serial data stream that receives low frequency and high frequency test tones, accurately measures an amount of attenuation experienced by the high frequency test tone in relation to the low frequency test tone, and accordingly, produces equalization data that results in a corresponding amount of equalization or pre-emphasis being added to an outgoing signal. More specifically, however, the present invention includes both open loop and closed loop systems for equalizing or adding pre-emphasis to a signal with attenuation. In the open loop transceiver system, a presumption is made that an amount of attenuation in both the outgoing and ingoing directions are equal. In the closed loop transceiver system, a receiver determines an amount of equalization and produces the equalization data to a remote transceiver.
摘要翻译： 用于均衡接收低频和高频测试音的高数据速率串行数据流的电路，精确地测量与低频测试音相关的高频测试音经历的衰减量，并因此产生结果的均衡数据 在相应的均衡或预加重量被加到输出信号上。 然而，更具体地，本发明包括用于均衡或增加具有衰减的信号的预加重的开环和闭环系统。 在开环收发器系统中，假设输出和进入方向上的衰减量相等。 在闭环收发机系统中，接收机确定均衡量，并向远程收发器产生均衡数据。
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6.发明授权Methods and apparatus for device-specific configuration of a programmable integrated circuit 有权可编程集成电路器件特定配置的方法和装置公开(公告)号：US07902863B1
公开(公告)日：2011-03-08
申请号：US12049189
申请日：2008-03-14
IPC分类号： H03K19/173
CPC分类号： H03K19/17748 , G06F17/5054
摘要： Methods and apparatus for configuring a programmable integrated circuit are described. In one example, a configuration stream having first data for programming first locations in a configuration memory and an instruction for referencing circuitry in the programmable integrated circuit is received. Second data is obtained from the circuitry based on the instruction. Second locations in the configuration memory are programmed in response to the second data.
摘要翻译： 描述用于配置可编程集成电路的方法和装置。 在一个示例中，接收具有用于对配置存储器中的第一位置进行编程的第一数据和用于参考可编程集成电路中的电路的指令的配置流。 基于该指令的电路获得第二数据。 响应于第二数据对配置存储器中的第二位置进行编程。
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公开(公告)号：US07336755B1
公开(公告)日：2008-02-26
申请号：US10864241
申请日：2004-06-08
申请人： David E. Tetzlaff
发明人： David E. Tetzlaff
IPC分类号： H03D3/24
CPC分类号： H03L7/18
摘要： A phase-locked loop with a non-integer divider utilizes a state machine to periodically select a new clock from a plurality of clocks for comparison to a reference signal after division by an integer divide by N block. Based on a desired divider ratio, the state machine selects the new clock that is phase shifted with respect to a presently selected clock. Each change from the presently selected clock to the new clock produces a selected clock cycle that is expanded or contracted by the amount of phase shift between the new clock and the presently selected clock. The integer divide by N block divides the selected clock by the integer portion of the desired divider ratio producing a divided clock that is effectively divided by a non-integer amount.
摘要翻译： 具有非整数分频器的锁相环使用状态机从多个时钟周期性地选择新时钟，以便在除以N个块之后除以参考信号。 基于期望的分频比，状态机选择相对于当前选择的时钟相移的新时钟。 从当前选择的时钟到新时钟的每个变化产生选择的时钟周期，该时钟周期由新时钟和当前选择的时钟之间的相移量扩大或缩小。 整数除以N个块将所选择的时钟除以所需分频比的整数部分，产生有效除以非整数的分频时钟。
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公开(公告)号：US5936514A
公开(公告)日：1999-08-10
申请号：US720120
申请日：1996-09-27
申请人： Stephen D. Anderson , Theodore L. Johnson , Brian S. Junk , Michael A. Orman , Theodore H. Schnaare , David E. Tetzlaff
发明人： Stephen D. Anderson , Theodore L. Johnson , Brian S. Junk , Michael A. Orman , Theodore H. Schnaare , David E. Tetzlaff
CPC分类号： H02M7/219 , G08C19/02 , Y10T307/858 , Y10T307/865
摘要： A field instrument includes an input circuit having a transistor bridge rectifier which is couplable to a power supply. The transistor bridge rectifier is configured to provide power from the power supply to a remainder of the field instrument.
摘要翻译： 现场仪表包括具有可与电源耦合的晶体管桥式整流器的输入电路。 晶体管桥式整流器被配置为从电源向现场仪器的其余部分提供电力。
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公开(公告)号：US5909188A
公开(公告)日：1999-06-01
申请号：US805128
申请日：1997-02-24
申请人： David E. Tetzlaff , James P. Ross
发明人： David E. Tetzlaff , James P. Ross
摘要： A transmitter for use in a process control setting includes a sensor adapted to couple to a process and provide a sensor output related to a parameter of the process. A modulator coupled to the sensor output responsively provides a digital bit stream output representative of the sensor output. A filter provides a current decimation output. A comparator compares a previous decimation output with the current decimation output. Circuitry is provided for transmitting an output related to the parameter based upon the current decimation.
摘要翻译： 用于过程控制设置的发射器包括适于耦合到过程的传感器，并提供与过程参数相关的传感器输出。 耦合到传感器输出的调制器响应地提供表示传感器输出的数字比特流输出。 滤波器提供电流抽取输出。 比较器将先前的抽取输出与当前的抽取输出进行比较。 提供电路，用于基于当前抽取发送与参数有关的输出。
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公开(公告)号：US5928345A
公开(公告)日：1999-07-27
申请号：US723688
申请日：1996-09-30
IPC分类号： G05B15/02 , G05B19/042 , G05B19/418 , G06F13/00
CPC分类号： G05B19/0421 , G05B15/02 , G05B19/4185 , G05B2219/25145 , Y02P90/18
摘要： The present invention includes a process control instrument having an improved data bus protocol for facilitating communications between master and slave nodes. The process control instrument includes a microprocessor operating in accordance with the SPI data bus protocol, first and second peripheral devices, and a data bus coupled to the microprocessor and the first and second peripheral devices. The improved data bus protocol used in the process control instruments of the present invention provides numerous advantages such as reduced printed circuit board space requirements and greater interchangeability of peripheral and master node components.
摘要翻译： 本发明包括具有改进的数据总线协议以便于主节点与从节点之间的通信的过程控制装置。 过程控制仪器包括根据SPI数据总线协议操作的微处理器，第一和第二外围设备以及耦合到微处理器和第一和第二外围设备的数据总线。 在本发明的过程控制仪器中使用的改进的数据总线协议提供了许多优点，例如减少了印刷电路板空间要求以及外围和主节点组件的更大可互换性。
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