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    Nitride disposable spacer to reduce mask count in CMOS transistor formation
    2.
    发明授权
    Nitride disposable spacer to reduce mask count in CMOS transistor formation 有权
    氮化物一次性间隔物，以减少CMOS晶体管形成中的掩模数

    公开(公告)号：US6103563A

    公开(公告)日：2000-08-15

    申请号：US271290

    申请日：1999-03-17

    申请人： Todd Lukanc ,  Raymond T. Lee ,  Zicheng Gary Ling

    发明人： Todd Lukanc ,  Raymond T. Lee ,  Zicheng Gary Ling

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823864

    摘要： Semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable nitride spacers on the sidewalls of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the disposable spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining disposable spacers are removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By using disposable spacers, the critical masking steps for source/drain ion implantation can be reduced to two, thereby reducing production costs and increasing manufacturing throughput.

    摘要翻译： 使用最少数量的临界掩模，在半导体衬底上形成不同导电类型的半导体器件。 实施例包括在半导体衬底的主表面上形成导电栅极，以及在栅极的侧壁上形成一次性氮化物间隔物。 然后在主要表面的浇口和部分上形成光致抗蚀剂掩模，以便植入第一导电类型的杂质。 然后在衬底中形成第二杂质类型的中等或重的源/漏植入物，然后去除未屏蔽的栅极上的一次性间隔物，并且在衬底中形成第二杂质类型的轻度或中等掺杂的源极/漏极延伸植入物 。 然后去除第一掩模，并且在主表面的先前未覆盖的浇口和注入部分上形成第二光致抗蚀剂掩模。 然后形成具有第一导电类型的杂质的中等或重的源极/漏极植入物，剩余的一次性间隔物被去除，并形成第一导电类型的轻度或中等掺杂的源极/漏极延伸植入物。 通过使用一次性间隔件，用于源/漏离子注入的关键掩蔽步骤可以减少到两个，从而降低生产成本并提高制造生产能力。

    Method for self-aligning polysilicon gates with field isolation and the resultant structure
    4.
    发明授权
    Method for self-aligning polysilicon gates with field isolation and the resultant structure 失效
    使用场隔离自对准多晶硅栅极的方法及其结果

    公开(公告)号：US6046088A

    公开(公告)日：2000-04-04

    申请号：US985400

    申请日：1997-12-05

    申请人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

    发明人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Craig S. Sander ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/762

    CPC分类号： H01L21/28123 ,  H01L21/76224 ,  H01L29/6659

    摘要： A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.

    摘要翻译： 在诸如浅​​氧化物沟槽的半导体衬底（例如浅氧化物沟槽）中形成场隔离的方法，用于隔离包括互补FET（例如CMOS）的FET晶体管，所述沟槽的选定部分在衬底上延伸并与随后形成的上表面共面 多晶硅门 在沟槽开口的形成和填充期间使用蚀刻保护层，使得沟槽的顶部与蚀刻保护层的上表面共面。 在将非掩蔽沟槽平坦化到蚀刻保护层的底部边缘之前，将沟槽的选定部分进行掩模和保护。 在多晶硅的沉积和平坦化之后，用于形成FET晶体管的多晶硅栅极的沉积多晶硅层的上表面与场隔离沟槽的向上延伸的选定部分是共面的和自对准的。

    Aluminum disposable spacer to reduce mask count in CMOS transistor formation
    6.
    发明授权
    Aluminum disposable spacer to reduce mask count in CMOS transistor formation 失效
    铝一次性间隔物，以减少CMOS晶体管形成中的掩模数量

    公开(公告)号：US06221706B1

    公开(公告)日：2001-04-24

    申请号：US09268713

    申请日：1999-03-17

    申请人： Todd Lukanc ,  Raymond T. Lee ,  Zicheng Gary Ling ,  Matthew S. Buynoski

    发明人： Todd Lukanc ,  Raymond T. Lee ,  Zicheng Gary Ling ,  Matthew S. Buynoski

    IPC分类号： H01L218238

    CPC分类号： H01L21/823864

    摘要： MOS semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable aluminum sidewall spacers on the side surfaces of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the aluminum sidewall spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface. Moderate or heavy source/drain implants with impurities of the first conductivity type are then formed, the remaining aluminum sidewall spacers are removed, and lightly or moderately doped source/drain extension implants of the first conductivity type formed. By using disposable aluminum sidewall spacers, which can be easily formed and removed without damage to other structures on the substrate or to the substrate silicon, the critical masking steps for source/drain ion implantation can be reduced to two, thereby reducing production costs and increasing manufacturing throughput.

    摘要翻译： 使用最少数量的临界掩模，在半导体衬底上形成不同导电类型的MOS半导体器件。 实施例包括在半导体衬底的主表面上形成导电栅极和在栅极的侧表面上的一次性铝侧壁间隔物。 然后在主要表面的浇口和部分上形成光致抗蚀剂掩模，以便植入第一导电类型的杂质。 然后在衬底中形成第二杂质类型的中等或重的源/漏植入物，然后去除未屏蔽的栅极上的铝侧壁间隔物，并且在第二杂质类型中形成轻度或中度掺杂的第二杂质类型的源极/漏极延伸植入物 基质。 然后去除第一掩模，并且在主表面的先前未覆盖的浇口和注入部分上形成第二光致抗蚀剂掩模。 然后形成具有第一导电类型的杂质的中等或重的源/漏植入物，除去剩余的铝侧壁间隔物，形成第一导电类型的轻度或中度掺杂的源极/漏极延伸植入物。 通过使用可以容易地形成和去除而不损坏衬底或衬底硅上的其它结构的一次性铝侧壁间隔物，用于源/漏离子注入的关键掩蔽步骤可以减少到两个，从而降低生产成本并增加 制造吞吐量。

    Forming minimal size spaces in integrated circuit conductive lines
    7.
    发明授权
    Forming minimal size spaces in integrated circuit conductive lines 失效
    在集成电路导线中形成最小尺寸空间

    公开(公告)号：US5930659A

    公开(公告)日：1999-07-27

    申请号：US986098

    申请日：1997-12-05

    申请人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

    发明人： Richard K. Klein ,  Asim A. Selcuk ,  Nicholas J. Kepler ,  Christopher A. Spence ,  Raymond T. Lee ,  John C. Holst ,  Stephen C. Horne

    IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/324

    CPC分类号： H01L21/76888 ,  H01L21/32105 ,  H01L21/76838

    摘要： A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to selectively ion implant oxygen into the polysilicon and annealing to convert the oxygen implanted polysilicon to silicon oxide. As an alternative method, an opening in an insulating layer overlying the conductive line is first formed by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening and using the sidewalls as a mask to blanket implant oxygen through the reduced opening and into the exposed polysilicon conductive line. After annealing, the implanted polysilicon converted to silicon oxide and removed to form a gap or space in the polysilicon conductive line pattern substantially equal in size to the reduced opening. Instead of blanket implanting with oxygen, thermal oxidation can be used to convert the exposed polysilicon to silicon oxide.

    摘要翻译： 通过将多晶硅中期望的间隙或空间的大小的面积转换为氧化硅，然后除去氧化硅，形成多晶硅导电线图形中的最小间隙或间隔的方法，以增加集成电路的密度。 优选的方法是选择性地将氧注入到多晶硅中并进行退火以将氧注入的多晶硅转化为氧化硅。 作为替代方法，首先通过常规光学光刻形成覆盖在导电线上的绝缘层中的开口，随后在开口中形成侧壁以形成减小的开口，并且使用侧壁作为掩模，以通过缩小开口来覆盖氧气注入氧气 并进入暴露的多晶硅导电线。 在退火之后，注入的多晶硅转变成氧化硅并去除，以在多晶硅导电线图案中形成与缩小的开口大致相等的间隙或空间。 代替用氧气进行全面注入，可以使用热氧化来将暴露的多晶硅转化为氧化硅。

    Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers
    8.
    发明授权
    Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers 失效
    减少屏蔽步骤使用可移动的非晶硅侧壁间隔物形成CMOS晶体管

    公开(公告)号：US06479350B1

    公开(公告)日：2002-11-12

    申请号：US09639814

    申请日：2000-08-17

    申请人： Zicheng Gary Ling ,  Todd Lukanc ,  Raymond T. Lee

    发明人： Zicheng Gary Ling ,  Todd Lukanc ,  Raymond T. Lee

    IPC分类号： H01L21336

    CPC分类号： H01L29/6653 ,  H01L21/823814 ,  H01L21/823864

    摘要： CMOS semiconductor devices comprising MOS transistors of different channel conductivity type are formed in or on a common semiconductor substrate using a minimum number of critical masks. Embodiments include forming conductive gate/insulator layer stacks on spaced-apart, different conductivity portions of the main surface of the substrate, forming etch-resistant inner sidewall spacers on side surfaces of the layer stacks, and forming easily etched, amorphous semiconductor disposable outer sidewall spacers on the inner sidewall spacers. The use of disposable outer sidewall spacers allows heavy and light source/drain implantations of opposite conductivity type to be performed for forming PMOS and NMOS transistors with the use of only two critical masks, thereby reducing production cost and duration, while increasing manufacturing throughput.

    摘要翻译： 包含不同沟道导电类型的MOS晶体管的CMOS半导体器件使用最少数量的临界掩模形成在公共半导体衬底中或上。 实施例包括在衬底的主表面的间隔开的不同导电部分上形成导电栅极/绝缘体层堆叠，在层堆叠的侧表面上形成耐腐蚀的内侧壁间隔物，以及形成容易蚀刻的非晶半导体一次性外侧壁 内侧壁间隔件上的间隔件。 使用一次性外侧壁间隔件可以实现相反导电类型的重和光源/漏极注入，以便仅使用两个临界掩模来形成PMOS和NMOS晶体管，从而降低生产成本和持续时间，同时提高制造吞吐量。

    Two step mask process to eliminate gate end cap shortening
    9.
    发明授权
    Two step mask process to eliminate gate end cap shortening 有权
    两步掩模过程，以消除门帽缩短

    公开(公告)号：US06287904B1

    公开(公告)日：2001-09-11

    申请号：US09499047

    申请日：2000-02-07

    申请人： Raymond T. Lee ,  Zicheng Gary Ling

    发明人： Raymond T. Lee ,  Zicheng Gary Ling

    IPC分类号： H01L21336

    CPC分类号： H01L29/4238 ,  H01L21/28123

    摘要： Metal oxide semiconductor devices are formed having gates with minimum endcap width and no source/drain leakage. A pair of source/drain regions is formed in a substrate, and a gate oxide is formed on the substrate. A layer of a conductive material, such as polysilicon, is formed on the gate oxide layer, masked and etched to form an extended-width gate having endcaps of a greater width than the endcap design rules. A second mask is formed to cover the extended-width gate up to the desired width of the endcaps (i.e., the design width) and to expose the portions of the extended-width gate beyond the endcap design width. The exposed portions of the extended-width gate are then etched, resulting in a completed gate having endcaps of the design width. Since the endcaps are initially formed to a greater width than the design width, any pullback that occurs during printing of the mask or etching of the gate does not cause the gate to be insufficiently wide to avoid source/drain leakage. Since the excess endcap material is removed, adjacent features and/or devices can be densely spaced on the substrate.

    摘要翻译： 金属氧化物半导体器件形成为具有最小端盖宽度且没有源漏漏极的栅极。 在衬底中形成一对源极/漏极区，并且在衬底上形成栅极氧化物。 在栅极氧化物层上形成诸如多晶硅的导电材料层，被掩模和蚀刻以形成具有比端盖设计规则更大宽度的端盖的延伸宽度门。 形成第二掩模以将延伸宽度的栅极覆盖直到端盖的期望宽度（即，设计宽度），并且将扩展宽度栅极的部分暴露超过端盖设计宽度。 然后对扩展宽度栅极的暴露部分进行蚀刻，得到具有设计宽度的端盖的完成的栅极。 由于端盖最初形成为比设计宽度更大的宽度，所以在印刷掩模或蚀刻栅极期间发生的任何回退都不会导致栅极不够宽以避免源/漏泄漏。 由于去除多余的端盖材料，相邻的特征和/或器件可以在基底上密集地间隔开。