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    Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction
    2.
    发明授权
    Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction 有权
    用于绝缘局部互连的方法和布置，以改善对准公差和减小尺寸

    公开(公告)号：US06399480B1

    公开(公告)日：2002-06-04

    申请号：US09515319

    申请日：2000-02-29

    申请人： William G. En ,  Darin A. Chan ,  David K. Foote ,  Fei Wang ,  Minh Van Ngo

    发明人： William G. En ,  Darin A. Chan ,  David K. Foote ,  Fei Wang ,  Minh Van Ngo

    IPC分类号： H01L714263

    CPC分类号： H01L21/76895 ,  H01L21/76897

    摘要： At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting,the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.

    摘要翻译： 在晶体管布置内提供至少一个图案化的介电层，以防止局部互连在形成局部互连的蚀刻开口的镶嵌层形成期间由于不对准导致栅极导体电接触。 通过在局部互连蚀刻工艺期间通过选择性蚀刻穿过多个电介质层，将图案化的介电层留在原位以防止栅极短路到相邻的局部互连，其稍微错位。

    Silicon oxime spacer for preventing over-etching during local interconnect formation
    7.
    发明授权
    Silicon oxime spacer for preventing over-etching during local interconnect formation 失效
    硅肟间隔物，用于在局部互连形成期间防止过蚀刻

    公开(公告)号：US5990524A

    公开(公告)日：1999-11-23

    申请号：US993868

    申请日：1997-12-18

    申请人： William G. En ,  Minh Van Ngo ,  Chih-Yuh Yang ,  David K. Foote ,  Scott A. Bell ,  Olov B. Karlsson ,  Christopher F. Lyons

    发明人： William G. En ,  Minh Van Ngo ,  Chih-Yuh Yang ,  David K. Foote ,  Scott A. Bell ,  Olov B. Karlsson ,  Christopher F. Lyons

    IPC分类号： H01L21/768 ,  H01L29/78

    CPC分类号： H01L21/76897 ,  H01L21/76895

    摘要： During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying dielectric layers. A punch-through region can damage the transistor circuit. Improved, multipurpose spacers are provided to reduce the chances of over-etching. The multipurpose spacers are made of silicon oxime. The etching plasmas that are used to etch one or more overlying dielectric layers tend to have a higher selectivity ratio to the multipurpose spacers than to the conventional oxide spacers. Additionally, the multipurpose spacers do not tend to degrade the hot carrier injection (HCI) properties as would a typical nitride spacer.

    摘要翻译： 在半导体晶片中局部互连的镶嵌形成期间，由于将与晶体管栅极相邻的氧化物间隔物暴露于用于蚀刻一个或多个蚀刻等离子体的一个或多个蚀刻等离子体，可以将穿透区域形成为衬底， 更重叠的电介质层。 穿通区域可能会损坏晶体管电路。 提供改进的多用途间隔件以减少过度蚀刻的机会。 多用途间隔件由硅肟制成。 用于蚀刻一个或多个上覆电介质层的蚀刻等离子体与常规氧化物间隔物相比往往具有比多用途间隔物更高的选择比。 此外，多用途间隔物不会像典型的氮化物间隔物一样降低热载流子注入（HCl）性质。

    Deposition control of stop layer and dielectric layer for use in the formation of local interconnects
    8.
    发明授权
    Deposition control of stop layer and dielectric layer for use in the formation of local interconnects 失效
    用于形成局部互连的停止层和介电层的沉积控制

    公开(公告)号：US6060393A

    公开(公告)日：2000-05-09

    申请号：US993888

    申请日：1997-12-18

    申请人： Minh Van Ngo ,  Darin A. Chan ,  David K. Foote

    发明人： Minh Van Ngo ,  Darin A. Chan ,  David K. Foote

    IPC分类号： H01L21/768 ,  H01L21/304

    CPC分类号： H01L21/76895 ,  H01L21/76801

    摘要： A deposition method allows for the forming of a uniform dielectric stop layer that is substantially void of defects caused by outgassing effects. The stop layer is deposited in a reactor chamber at a higher than normal temperature of at least 480.degree. C. The stop layer is then combined with an overlying dielectric layer to provide an inter-level dielectric structure through which a local interconnect can be formed to provide a conductive path to one or more regions of the underlying semiconductor devices.

    摘要翻译： 沉积方法允许形成基本上没有由除气效应引起的缺陷的均匀的电介质停止层。 停止层沉积在高于至少480℃的常温的反应器室中。然后将停止层与覆盖的介电层组合以提供层间电介质结构，通过该层间电介质结构可以形成局部互连 为下面的半导体器件的一个或多个区域提供导电路径。

    Methods for making a semiconductor device with improved hot carrier lifetime
    9.
    发明授权
    Methods for making a semiconductor device with improved hot carrier lifetime 失效
    制造具有改善的热载流子寿命的半导体器件的方法

    公开(公告)号：US6022799A

    公开(公告)日：2000-02-08

    申请号：US993828

    申请日：1997-12-18

    申请人： David K. Foote ,  Minh Van Ngo ,  Darin A. Chan

    发明人： David K. Foote ,  Minh Van Ngo ,  Darin A. Chan

    IPC分类号： H01L21/027 ,  H01L21/312 ,  H01L21/314 ,  H01L21/768 ,  H01L21/8247

    CPC分类号： H01L21/76895 ,  H01L21/0276 ,  H01L21/3121 ,  H01L21/3145

    摘要： A local interconnection to a device region in/on a substrate is formed by depositing either silicon oxynitride or silicon oxime as an etch stop layer, at a temperature of less than about 480.degree. C. to increase the hot carrier injection (HCI) lifetime of the resulting semiconductor device. A dielectric layer is then deposited over the etch stop layer and through-holes are etched exposing the etch stop layer using a first etching process. A second etching process is then conducted, which etches through the etch stop layer exposing at least one device region. The resulting through-hole is then filled with conductive material(s) to form a local interconnection.

    摘要翻译： 通过在小于约480℃的温度下沉积硅氧氮化物或硅肟作为蚀刻停止层来形成与衬底中/之上的器件区域的局部互连，以增加热载流子注入（HCI）寿命 得到的半导体器件。 然后将介电层沉积在蚀刻停止层上，并且使用第一蚀刻工艺蚀刻暴露蚀刻停止层的通孔。 然后进行第二蚀刻工艺，其蚀刻通过蚀刻停止层暴露至少一个器件区域。 然后将所形成的通孔用导电材料填充以形成局部互连。

    Gate pattern formation using a bottom anti-reflective coating
    10.
    发明授权
    Gate pattern formation using a bottom anti-reflective coating 失效
    使用底部抗反射涂层的栅格图案形成

    公开(公告)号：US5963841A

    公开(公告)日：1999-10-05

    申请号：US924370

    申请日：1997-09-05

    申请人： Olov B. Karlsson ,  Christopher F. Lyons ,  Minh Van Ngo ,  Scott A. Bell ,  David K. Foote

    发明人： Olov B. Karlsson ,  Christopher F. Lyons ,  Minh Van Ngo ,  Scott A. Bell ,  David K. Foote

    IPC分类号： H01L21/3213 ,  H01L21/302

    CPC分类号： H01L21/32139

    摘要： A gate is formed on a semiconductor substrate by using a bottom anti-reflective coating (BARC) to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, a SiON BARC over the conductive layer, a thin oxide film over the SiON BARC. The resist mask is formed on the oxide film. The SiON BARC improves the resist mask formation process. The wafer stack is then shaped to form one or more polysilicon gates by sequentially etching through selected portions of the oxide film, the BARC, and the gate conductive layer as defined by the etch windows in the resist mask. Once properly shaped, the remaining portions of the resist mask, oxide film and SiON BARC are removed.

    摘要翻译： 通过使用底部抗反射涂层（BARC）在半导体衬底上形成栅极以更好地控制通过形成在其上的深UV抗蚀剂掩模所限定的栅极的临界尺寸（CD）。 晶片堆叠包括半导体衬底上的栅极氧化物层，栅极氧化物层上的多晶硅栅极层，导电层上的SiON BARC，SiON BARC上的薄氧化物膜。 在氧化物膜上形成抗蚀剂掩模。 SiON BARC改进了抗蚀剂掩模形成过程。 然后通过依次蚀刻通过抗蚀剂掩模中由蚀刻窗口限定的氧化膜，BARC和栅极导电层的选定部分，将晶片堆叠成形以形成一个或多个多晶硅栅极。 一旦适当成形，就去除了抗蚀剂掩模，氧化膜和SiON BARC的其余部分。