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40 条记录 (耗时 0.028 秒)

    Method and circuit for hot swap protection
    1.
    发明授权
    Method and circuit for hot swap protection 有权
    热插拔保护方法和电路

    公开(公告)号：US06810458B1

    公开(公告)日：2004-10-26

    申请号：US10090257

    申请日：2002-03-01

    申请人： Hassan K. Bazargan ,  Jian Tan ,  Atul V. Ghia ,  Suresh M. Menon

    发明人： Hassan K. Bazargan ,  Jian Tan ,  Atul V. Ghia ,  Suresh M. Menon

    IPC分类号： G06F1300

    CPC分类号： G06F13/4081

    摘要： A hot swap protection circuit (40) for an integrated circuit being plugged into a powered-up system includes a first circuit (10) for detecting a hot swap condition, a second circuit (20) coupled to the first circuit for preventing a pn junction diode (52) in a pull-up transistor (32) from going into a forward bias condition, and a third circuit (30) coupled to the first and second circuits for preventing the pull-up transistor from turning on during the hot swap condition.

    摘要翻译： 用于插入加电系统的集成电路的热插拔保护电路（40）包括用于检测热插拔状态的第一电路（10），耦合到第一电路的第二电路（20），用于防止pn结 上拉晶体管（32）中的二极管（52）进入正向偏置状态，以及耦合到第一和第二电路的第三电路（30），用于防止在热插拔条件期间上拉晶体管导通 。

    Circuit for producing low-voltage differential signals
    6.
    发明授权
    Circuit for producing low-voltage differential signals 有权
    用于生成低压差分信号的电路

    公开(公告)号：US06366128B1

    公开(公告)日：2002-04-02

    申请号：US09655168

    申请日：2000-09-05

    申请人： Atul V. Ghia ,  Suresh M. Menon ,  David P. Schultz

    发明人： Atul V. Ghia ,  Suresh M. Menon ,  David P. Schultz

    IPC分类号： H03K19094

    CPC分类号： H04L25/0272 ,  H03K5/151 ,  H03K19/018528 ,  H04L25/028

    摘要： Described are systems for producing differential logic signals. These systems can be adapted for use with different loads by programming one or more programmable elements. One embodiment includes a series of driver stages, the outputs of which are connected to one another. The driver stages turn on successively to provide increasingly powerful differential amplification. This progressive increase in amplification produces a corresponding progressive decrease in output resistance, which reduces the noise associated with signal reflection. The systems can be incorporated into programmable IOBs to enable PLDs to provide differential output signals.

    摘要翻译： 描述了用于产生差分逻辑信号的系统。 这些系统可以通过编程一个或多个可编程元件而适用于不同的负载。 一个实施例包括一系列驱动级，其输出彼此连接。 驱动器阶段依次打开，提供越来越强大的差分放大。 放大的逐渐增加产生输出电阻的相应逐渐降低，这降低了与信号反射相关联的噪声。 这些系统可以并入可编程IOB中，以使PLD能够提供差分输出信号。

    Configuration memory architecture for FPGA
    7.
    发明授权
    Configuration memory architecture for FPGA 失效
    FPGA配置存储器架构

    公开(公告)号：US06222757B1

    公开(公告)日：2001-04-24

    申请号：US09030616

    申请日：1998-02-25

    申请人： Prasad Rau ,  Atul V. Ghia ,  Suresh M. Menon

    发明人： Prasad Rau ,  Atul V. Ghia ,  Suresh M. Menon

    IPC分类号： G11C1100

    CPC分类号： H03K19/1776

    摘要： A configuration memory architecture for an FPGA that eliminates the need for a regular array of word lines and bit lines is disclosed. The memory is comprised, in the preferred embodiment, of a plurality of memory bytes. Each memory byte has eight SRAM latches, a single flip flop and a one-of-eight decoder having a data input coupled to the inverting output of the flip flop and eight individual data outputs, each of which is coupled to a data input of one of the SRAM latches. The decoder also has address and write control inputs which are coupled to a state machine or other programmable device that controls the sequencing of the loading operation to load configuration data into the memory. The flip flops of all the memory bytes are coupled together in a serpentine shift register. Loading of configuration data involves shutting all paths through the decoder down, shifting all configuration bits for the “0” position SRAM latch of each memory byte into the shift register, and setting the address bits to the decoder so as to create a conductive path in each memory byte from the output of the flip flop to the data input of the selected SRAM latch. The process is then repeated for all other SRAM latches.

    摘要翻译： 公开了一种用于FPGA的配置存储器架构，其不需要常规的字线和位线阵列。 在优选实施例中，存储器包括多个存储器字节。 每个存储器字节具有八个SRAM锁存器，单个触发器和八分之一解码器，其具有耦合到触发器的反相输出的数据输入和八个单独的数据输出，每个独立数据输出耦合到一个的数据输入 的SRAM锁存器。 解码器还具有地址和写控制输入，其耦合到状态机或其他可编程设备，其控制加载操作的顺序以将配置数据加载到存储器中。 所有存储器字节的触发器在蛇形移位寄存器中耦合在一起。 配置数据的加载涉及关闭通过解码器的所有路径向下移动，将每个存储器字节的“0”位SRAM锁存器的所有配置位移动到移位寄存器中，并将地址位设置为解码器，以便在 每个存储器字节从触发器的输出到所选SRAM锁存器的数据输入。 然后对所有其他SRAM锁存器重复该过程。

    Integrated circuit having embedded differential clock tree
    8.
    发明授权
    Integrated circuit having embedded differential clock tree 有权
    集成电路具有嵌入式差分时钟树

    公开(公告)号：US07759973B1

    公开(公告)日：2010-07-20

    申请号：US12174502

    申请日：2008-07-16

    申请人： Vasisht Mantra Vadi ,  Steven P. Young ,  Atul V. Ghia ,  Adebabay M. Bekele ,  Suresh M. Menon

    发明人： Vasisht Mantra Vadi ,  Steven P. Young ,  Atul V. Ghia ,  Adebabay M. Bekele ,  Suresh M. Menon

    IPC分类号： H03K19/177

    CPC分类号： G06F1/10 ,  H03K5/15013 ,  H03K19/1774 ,  H03K19/17784 ,  H03K19/17796

    摘要： A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

    摘要翻译： 一种时钟分配网络，具有：骨干时钟信号线，被配置为提供差分时钟信号; 多个分支耦合到主干时钟信号线，用于将差分时钟信号分配给多个可编程功能元件; 耦合到第一分支的第一叶节点，其中所述第一叶节点被配置为将所述差分时钟信号提供给第一可编程功能元件; 以及耦合到第二分支的第二叶节点，其中所述第二叶节点被配置为将从所述差分时钟信号导出的单端时钟信号提供给第二可编程功能元件。

    Data alignment and deskewing module
    9.
    发明授权
    Data alignment and deskewing module 有权
    数据对齐和脱斜模块

    公开(公告)号：US07551646B1

    公开(公告)日：2009-06-23

    申请号：US10938151

    申请日：2004-09-10

    申请人： Qi Zhang ,  Jason R. Bergendahl ,  Atul V. Ghia ,  Suresh M. Menon

    发明人： Qi Zhang ,  Jason R. Bergendahl ,  Atul V. Ghia ,  Suresh M. Menon

    IPC分类号： H04J3/06

    CPC分类号： H04J3/0629

    摘要： A data alignment and deskewing module includes a delay calibration unit, a data alignment and deskew unit, and a delay unit. The delay calibration unit is operably coupled to generate a reference signal based on a reference clock and a mirrored delay line output signal. The data alignment and deskew unit is operably coupled to determine a delay selection signal based on a delayed and deskewed representation of an input data stream and propagation delay of a line on which the input data stream is received. The delay unit is operably coupled to produce the delayed and deskewed representation of the input data stream based on the reference signal and the delay selection signal.

    摘要翻译： 数据对准和去歪斜模块包括延迟校准单元，数据对准和去歪斜单元以及延迟单元。 延迟校准单元可操作地耦合以基于参考时钟和镜像延迟线输出信号产生参考信号。 数据对准和去歪斜单元可操作地耦合以基于输入数据流的延迟和偏斜校正表示以及接收输入数据流的线的传播延迟来确定延迟选择信号。 延迟单元可操作地耦合以基于参考信号和延迟选择信号产生输入数据流的延迟和去歪斜表示。

    Programmable logic device having an embedded differential clock tree
    10.
    发明授权
    Programmable logic device having an embedded differential clock tree 有权
    具有嵌入式差分时钟树的可编程逻辑器件

    公开(公告)号：US07414430B2

    公开(公告)日：2008-08-19

    申请号：US11511647

    申请日：2006-08-29

    申请人： Vasisht Mantra Vadi ,  Steven P. Young ,  Atul V. Ghia ,  Adebabay M. Bekele ,  Suresh M. Menon

    发明人： Vasisht Mantra Vadi ,  Steven P. Young ,  Atul V. Ghia ,  Adebabay M. Bekele ,  Suresh M. Menon

    IPC分类号： H03K19/177

    CPC分类号： G06F1/10 ,  H03K5/15013 ,  H03K19/1774 ,  H03K19/17784 ,  H03K19/17796

    摘要： A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

    摘要翻译： 一种时钟分配网络，具有：骨干时钟信号线，被配置为提供差分时钟信号; 多个分支耦合到主干时钟信号线，用于将差分时钟信号分配给多个可编程功能元件; 耦合到第一分支的第一叶节点，其中所述第一叶节点被配置为将所述差分时钟信号提供给第一可编程功能元件; 以及耦合到第二分支的第二叶节点，其中所述第二叶节点被配置为将从所述差分时钟信号导出的单端时钟信号提供给第二可编程功能元件。