公开(公告)号：US06921704B1

公开(公告)日：2005-07-26

申请号：US10700557

申请日：2003-11-05

Applicant: David Wu ,  Akif Sultan ,  Bin Yu

Inventor： David Wu ,  Akif Sultan ,  Bin Yu

IPC: H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/76

CPC classification number: H01L21/764 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823878

Abstract: A method of forming a silicon-on-insulator semiconductor device including providing a substrate and forming a trench in the substrate, wherein the trench includes opposing side walls extending upwardly from a base of the trench. The method also includes depositing at least two insulating layers into the trench to form a shallow trench isolation structure, wherein an innermost of the insulating layers substantially conforms to the base and the two side walls of the trench and an outermost of the insulating layers spans the side walls of the trench so that a gap is formed between the insulating layers in the trench. The gap creates compressive forces within the shallow trench isolation structure, which in turn creates tensile stress within the surrounding substrate to enhance mobility of the device.

Abstract translation: 一种形成绝缘体上半导体器件的方法，包括提供衬底并在衬底中形成沟槽，其中沟槽包括从沟槽的基底向上延伸的相对的侧壁。 该方法还包括将至少两个绝缘层沉积到沟槽中以形成浅沟槽隔离结构，其中绝缘层的最内层基本上与基底一致并且沟槽的两个侧壁和绝缘层的最外层横跨 沟槽的侧壁，使得在沟槽中的绝缘层之间形成间隙。 间隙在浅沟槽隔离结构内产生压缩力，这反过来在周围的衬底内产生拉伸应力，以增强器件的移动性。

公开(公告)号：US06979635B1

公开(公告)日：2005-12-27

申请号：US10759171

申请日：2004-01-20

Applicant: Akif Sultan ,  Qi Xiang ,  Bin Yu

Inventor： Akif Sultan ,  Qi Xiang ,  Bin Yu

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/28035 ,  H01L21/28123 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/976

Abstract: Ultra narrow and thin polycrystalline silicon gate electrodes are formed by patterning a polysilicon gate precursor, reducing its width and height by selectively oxidizing its upper and side surfaces, and then removing the oxidized surfaces. Embodiments include patterning the polysilicon gate precursor with an oxide layer thereunder, ion implanting to form deep source/drain regions, forming a nitride layer on the substrate surface on each side of the polysilicon gate precursor, thermally oxidizing the upper and side surfaces of the polysilicon gate precursor thereby consuming silicon, and then removing the oxidized upper and side surfaces leaving a polysilicon gate electrode with a reduced width and a reduced height. Subsequent processing includes forming shallow source/drain extensions, forming dielectric sidewall spacers on the polysilicon gate electrode and then forming metal silicide layers on the upper surface of the polysilicon gate electrode and over the source/drain regions.

Abstract translation: 通过图案化多晶硅栅极前体，通过选择性地氧化其上表面和侧表面，然后去除氧化表面而减小其宽度和高度来形成超窄和多晶硅栅电极。 实施例包括用其下面的氧化物层图案化多晶硅栅极前体，离子注入以形成深源极/漏极区域，在多晶硅栅极前体的每一侧的衬底表面上形成氮化物层，热氧化多晶硅的上表面和侧表面 从而消耗硅，然后去除氧化的上表面和侧表面，留下具有减小的宽度和降低的高度的多晶硅栅电极。 随后的处理包括形成浅源极/漏极延伸部分，在多晶硅栅电极上形成电介质侧壁间隔物，然后在多晶硅栅极电极的上表面上以及在源极/漏极区域上形成金属硅化物层。

公开(公告)号：US06777281B1

公开(公告)日：2004-08-17

申请号：US10214361

申请日：2002-08-08

Applicant: Daniel Kadosh ,  Scott D. Luning ,  Akif Sultan ,  David Wu

Inventor： Daniel Kadosh ,  Scott D. Luning ,  Akif Sultan ,  David Wu

IPC: H01L218238

CPC classification number: H01L29/6659 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/823814 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device, comprising steps of: (a) providing a semi conductor substrate including at least one dopant species-containing region extending to a surface of the substrate; (b) forming a thin liner oxide layer on the surface of the substrate; and (c) incorporating in the thin line oxide layer at least one species which substantially prevents, or at least reduces, segregation therein of the dopant species arising from movement thereinto from the at least one dopant species-containing region.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：（a）提供半导体衬底，其包括至少一个延伸到衬底表面的含掺杂物种的区域;（b）在衬底的表面上形成薄的衬里氧化物层 基材; 和（c）在细线氧化物层中并入至少一种物质，其至少一种物质，其基本上防止或至少减少其中从至少一种含掺杂物种的区域移动而引起的掺杂物质的偏析。

公开(公告)号：US06727136B1

公开(公告)日：2004-04-27

申请号：US10273291

申请日：2002-10-18

Applicant: James F. Buller ,  Derick J. Wristers ,  David Wu ,  Akif Sultan

Inventor： James F. Buller ,  Derick J. Wristers ,  David Wu ,  Akif Sultan

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/7833

Abstract: A method of manufacturing a semiconductor device, comprising sequential steps of: (a) providing a semiconductor substrate including a pre-selected thickness strained lattice layer of a first semiconductor material at an upper surface thereof and an underlying layer of a second semiconductor material; and (b) introducing a dopant-containing species of one conductivity type into at least one pre-selected portion of the strained lattice layer of first semiconductor material to form a dopant-containing region therein with a junction at a depth substantially equal to the pre-selected thickness, wherein the second semiconductor material of the underlying layer inhibits diffusion thereinto of the dopant-containing species from the strained lattice layer, thereby controlling/limiting the depth of the junction to substantially the pre-selected thickness of the strained lattice layer.

Abstract translation: 一种制造半导体器件的方法，包括以下顺序的步骤：（a）提供半导体衬底，该半导体衬底在其上表面包括预先选定的第一半导体材料的应变晶格层和第二半导体材料的下层; 和（b）将含有一种导电类型的含掺杂剂的物质引入到第一半导体材料的应变晶格层的至少一个预先选择的部分中，以在其中形成含有掺杂剂的区域，其中接合部的深度基本上等于预先 - 选择的厚度，其中下层的第二半导体材料抑制来自应变晶格层的含掺杂剂物质的扩散，从而将结的深度控制/限制到基本上预应变晶格层的预选厚度。

公开(公告)号：US07598161B2

公开(公告)日：2009-10-06

申请号：US11861534

申请日：2007-09-26

Applicant: Jingrong Zhou ,  Mark Michael ,  Donna Michael, legal representative ,  David Wu ,  James F. Buller ,  Akif Sultan

Inventor： Jingrong Zhou ,  Mark Michael ,  David Wu ,  James F. Buller ,  Akif Sultan

IPC: H01L21/425

CPC classification number: H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1083

Abstract: The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.

Abstract translation: 本文描述的光晕植入技术采用在光晕掺杂剂轰击期间产生晕轮植入物阴影效应的光晕注入掩模。 第一晶体管器件结构和第二晶体管器件结构形成在晶片上，使得它们彼此正交地取向。 创建了常见的光晕注入掩模，其特征在于，在第一晶体管器件结构的扩散区域的晕圈注入期间防止第二晶体管器件结构的扩散区域的光晕注入，并且具有防止第 在第二晶体管器件结构的扩散区的晕圈注入期间的第一晶体管器件结构。 晶体管器件结构的正交取向和光晕注入掩模的图案消除了创建多个注入掩模以实现晶体管器件结构的不同阈值电压的需要。

公开(公告)号：US07761838B2

公开(公告)日：2010-07-20

申请号：US11861492

申请日：2007-09-26

Applicant: Zhonghai Shi ,  Mark Michael ,  Donna Michael, legal representative ,  David Wu ,  James F. Buller ,  Jingrong Zhou ,  Akif Sultan

Inventor： Zhonghai Shi ,  Mark Michael ,  David Wu ,  James F. Buller ,  Jingrong Zhou ,  Akif Sultan

IPC: G06F17/50 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/78 ,  H01L29/7843

Abstract: The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

Abstract translation: 本文所述的技术和技术涉及自动创建与半导体基晶体管器件一起使用的应力衬垫的光致抗蚀剂掩模。 应力衬垫掩模是利用自动设计工具生成的，其利用与晶片上的特征，器件和结构对应的布局数据。 产生的应力衬垫掩模（以及使用应力衬垫掩模制造的晶片）限定了延伸超出晶体管区域的边界并进入晶片的应力不敏感区域的应力衬垫覆盖区域。 延伸的应力衬垫通过提供额外的压缩/拉伸应力来进一步提高相应晶体管的性能。

公开(公告)号：US07638837B2

公开(公告)日：2009-12-29

申请号：US11861051

申请日：2007-09-25

Applicant: Akif Sultan ,  Mark Michael ,  Donna Michael, legal representative ,  David Wu

Inventor： Akif Sultan ,  Mark Michael ,  David Wu

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

Abstract: A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.

Abstract translation: 提供一种应力增强型半导体器件，其包括具有非活性区域和有源区域的衬底，覆盖有源区域的至少一部分的第一类型应力层和第二类型应力层。 有源区域包括限定有源区域的第一宽度的第一侧边缘和限定有源区域的第二宽度的第二侧边缘。 第二类应力层设置在活动区域​​的第二侧边缘附近。

公开(公告)号：US07176095B1

公开(公告)日：2007-02-13

申请号：US10790939

申请日：2004-03-01

Applicant: Akif Sultan ,  David Wu ,  Wen-Jie Qi ,  Mark Fuselier

Inventor： Akif Sultan ,  David Wu ,  Wen-Jie Qi ,  Mark Fuselier

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/6659 ,  H01L29/7833

Abstract: Methods of fabricating halo regions are provided. In one aspect, a method is provided of fabricating a first halo region and a second halo region for a circuit device of a first conductivity type and having a gate structure with first and second sidewalls. The first halo region of a second conductivity type is formed by implanting the substrate with impurities in a first direction toward the first sidewall of the gate structure. The second halo region of the second conductivity type is formed by implanting the substrate with impurities in a second direction toward the second sidewall of the gate structure. The first and second halo regions are formed without implanting impurities in a direction substantially perpendicular to the first and second directions.

Abstract translation: 提供制造晕圈的方法。 在一个方面，提供了一种制造用于第一导电类型的电路器件的第一卤素区域和第二卤素区域的方法，并具有具有第一和第二侧壁的栅极结构。 第二导电类型的第一晕区是通过沿着第一方向将杂质注入栅极结构的第一侧壁而形成的。 第二导电类型的第二晕区是通过向栅极结构的第二侧壁向第二方向注入具有杂质的衬底形成的。 形成第一和第二晕圈，而不在基本上垂直于第一和第二方向的方向上植入杂质。

公开(公告)号：US06864516B2

公开(公告)日：2005-03-08

申请号：US10085903

申请日：2002-02-28

Applicant: Andy Wei ,  Akif Sultan ,  David Wu

Inventor： Andy Wei ,  Akif Sultan ,  David Wu

IPC: H01L21/265 ,  H01L21/322 ,  H01L21/336 ,  H01L29/786 ,  H01L29/74

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/26593 ,  H01L21/3221 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78621

Abstract: Various circuit devices incorporating junction-traversing dislocation regions and methods of making the same are provided. In one aspect, a method of processing is provided that includes forming an impurity region in a device region of a semiconductor-on-insulator substrate. The impurity region defines a junction. A dislocation region is formed in the device region that traverses the junction. The dislocation region provides a pathway to neutralize charge lingering in a floating body of a device.

Abstract translation: 提供了结合穿越位错区域的各种电路装置及其制造方法。 一方面，提供了一种处理方法，其包括在绝缘体上半导体衬底的器件区域中形成杂质区域。 杂质区限定了一个结。 在穿过结的器件区域中形成位错区域。 位错区域提供了中和装置的浮体中滞留电荷的途径。

公开(公告)号：US08687417B2

公开(公告)日：2014-04-01

申请号：US11867743

申请日：2007-10-05

Applicant: Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Akif Sultan ,  Fred Hause ,  Donna Michael

Inventor： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Akif Sultan ,  Fred Hause

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/02 ,  G11C16/00

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

Abstract translation: 第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。 第一晶体管的电压阈值基于第一偏置电荷。 第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。 第二晶体管的电压阈值基于第二偏置电荷。