公开(公告)号：US07173846B2

公开(公告)日：2007-02-06

申请号：US10366499

申请日：2003-02-13

Applicant: Wen-Chin Lin ,  Denny D. Tang ,  Yu Der Chih

Inventor： Wen-Chin Lin ,  Denny D. Tang ,  Yu Der Chih

IPC: G11C11/00

CPC classification number: G11C11/16

Abstract: A new magnetic RAM cell device is achieved. The device comprisese, first, a MTJ cell comprising a free layer and a pinned layer separated by a dielectric layer. A reading switch is coupled between the free layer and a reading line. A writing switch is coupled between a first end of the pinned layer and a first writing line. A second end of the pinned layer is coupled to a second writing line. Architectures using MRAM cells are disclosed.

Abstract translation: 实现了新的磁性RAM单元装置。 该装置首先包括由电介质层分离的自由层和钉扎层的MTJ电池。 读取开关耦合在自由层和读取线之间。 写入开关耦合在固定层的第一端和第一写入线之间。 固定层的第二端耦合到第二写入线。 公开了使用MRAM单元的架构。

公开(公告)号：US07205632B2

公开(公告)日：2007-04-17

申请号：US10818009

申请日：2004-04-05

Applicant: Wen-Chin Lin ,  Denny D. Tang ,  Chao-Hsiung Wang

Inventor： Wen-Chin Lin ,  Denny D. Tang ,  Chao-Hsiung Wang

IPC: H01L29/00

CPC classification number: H01L21/263 ,  H01L27/0688 ,  H01L27/08

Abstract: A microelectronics device including a semiconductor device located at least partially over a substrate, a bombarded area located at least partially over the substrate and adjacent the semiconductor device, and a bombarded attenuator interposing the semiconductor device and the bombarded area.

Abstract translation: 一种微电子器件，包括至少部分地位于衬底上的半导体器件，至少部分地位于衬底上并且邻近半导体器件的轰击区域，以及插入半导体器件和被轰击区域的轰击衰减器。

公开(公告)号：US06985383B2

公开(公告)日：2006-01-10

申请号：US10689421

申请日：2003-10-20

Applicant: Denny D. Tang ,  Wen-Chin Lin

Inventor： Denny D. Tang ,  Wen-Chin Lin

IPC: G11C11/14 ,  G11C11/15 ,  G11C7/14

CPC classification number: G11C5/147 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C2211/5634

Abstract: A multilevel reference generator has a plurality of nonlinear standard resistive elements where each resistive element is biased at a constant level to develop a resultant level. The multilevel reference generator has a plurality of mirror sources. Each mirror source is in communication with the one of the plurality of resistive elements such that each mirror source receives the resultant level from the one standard resistive element and provides a mirrored replication of the resultant level. The multilevel reference generator has a plurality of reference level combining circuits. The reference level combining circuit includes a resultant level summing circuit that additively combines the first and second mirrored replication level and a level scaling circuit to create a scaling of the combined first and second mirrored replication levels to create the reference level.

Abstract translation: 多电平参考发生器具有多个非线性标准电阻元件，其中每个电阻元件被偏置在恒定电平以产生合成电平。 多电平参考发生器具有多个镜源。 每个反射镜源与多个电阻元件中的一个电阻元件相通，使得每个反射镜源从一个标准电阻元件接收合成电平，并提供所得电平的镜像复制。 多电平参考发生器具有多个参考电平组合电路。 参考电平组合电路包括相加地组合第一和第二镜像复制级别的电平求和电路和级别缩放电路，以创建组合的第一和第二镜像复制级别的缩放以创建参考电平。

公开(公告)号：US06909628B2

公开(公告)日：2005-06-21

申请号：US10366498

申请日：2003-02-13

Applicant: Wen-Chin Lin ,  Denny D. Tang ,  Yu Der Chih

Inventor： Wen-Chin Lin ,  Denny D. Tang ,  Yu Der Chih

IPC: G11C11/00 ,  G11C11/15 ,  G11C11/16 ,  H01L43/00 ,  H03K5/02

CPC classification number: G11C11/16

Abstract: A new magnetic RAM cell device is achieved. The device comprises a MTJ cell comprising a free layer and a pinned layer separated by a dielectric layer. A diode is coupled between the free layer and a reading line. A writing switch is coupled between a first end of the pinned layer and a first writing line. A second end of the pinned layer is coupled to a second writing line. Architectures using MRAM cells are disclosed.

Abstract translation: 实现了新的磁性RAM单元装置。 该器件包括MTJ电池，其包括由电介质层分离的自由层和钉扎层。 二极管耦合在自由层和读取线之间。 写入开关耦合在固定层的第一端和第一写入线之间。 固定层的第二端耦合到第二写入线。 公开了使用MRAM单元的架构。

公开(公告)号：US08153471B2

公开(公告)日：2012-04-10

申请号：US12945860

申请日：2010-11-14

Applicant: Li-Shyue Lai ,  Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin

Inventor： Li-Shyue Lai ,  Chao-Hsiung Wang ,  Denny Tang ,  Wen-Chin Lin

IPC: H01L21/06

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/1691

Abstract: A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current.

Abstract translation: 一种相变存储器结构及其形成方法，所述方法包括提供包括导电区域的衬底; 在间隔物的上部形成具有部分暴露的侧壁区域的间隔物，其限定相变存储元件接触区域; 并且其中所述间隔件底部部分与所述导电区域重叠。 这两种方法都可以减少相变存储元件的有效面积，从而减少所需的相变电流。

公开(公告)号：US07964900B2

公开(公告)日：2011-06-21

申请号：US12586688

申请日：2009-09-24

Applicant: Wen-Chin Lin ,  Denny Tang ,  Chuan-Ying Lee ,  Hsu Chen Cheng

Inventor： Wen-Chin Lin ,  Denny Tang ,  Chuan-Ying Lee ,  Hsu Chen Cheng

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/76 ,  H01L21/263 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/08

Abstract: A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.

Abstract translation: 半导体衬底包括在半导体子结构上形成的图案化硬掩模膜的开口下方的半绝缘部分，其厚度足以防止带电粒子通过硬掩模。 半绝缘部分包括带电粒子并且可以深深地延伸到半导体衬底中并且电绝缘形成在半绝缘部分的相对侧上的器件。 带电粒子可以有利地是质子，并且由图案化的硬掩模膜覆盖的另外的基底部分基本上没有带电粒子。

公开(公告)号：US07554145B2

公开(公告)日：2009-06-30

申请号：US11610760

申请日：2006-12-14

Applicant: Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

Inventor： Yuan-Hung Liu ,  Chih-Ta Wu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Wen-Chin Lin ,  Chia-Shiung Tsai

IPC: H01L29/76

CPC classification number: H01L43/12 ,  H01L27/228

Abstract: An improved magnetoresistive memory device has a reduced distance between the magnetic memory element and a conductive memory line used for writing to the magnetic memory element. The reduced distance is facilitated by forming the improved magnetoresistive memory device according to a method that includes forming a mask over the magnetoresistive memory element and forming an insulating layer over the mask layer, then removing portions of the insulating layer using a planarization process. A conductive via can then be formed in the mask layer, for example using a damascene process. The conductive memory line can then be formed over the mask layer and conductive via.

Abstract translation: 改进的磁阻存储器件具有减小的磁存储元件与用于写入磁存储器元件的导电存储器线之间的距离。 通过根据包括在磁阻存储元件上形成掩模并在掩模层上形成绝缘层，然后使用平坦化处理去除绝缘层的部分的方法，通过形成改进的磁阻存储器件来简化缩短的距离。 然后可以在掩模层中形成导电通孔，例如使用镶嵌工艺。 然后可以在掩模层和导电通孔上形成导电存储器线。

公开(公告)号：US20070091672A1

公开(公告)日：2007-04-26

申请号：US11610739

申请日：2006-12-14

Applicant: Wen-Chin Lin ,  Denny Tang ,  Li-Shyue Lai ,  Chao-Hsiung Wang ,  Fan-Shi Lai

Inventor： Wen-Chin Lin ,  Denny Tang ,  Li-Shyue Lai ,  Chao-Hsiung Wang ,  Fan-Shi Lai

IPC: G11C11/00

CPC classification number: G11C11/1673

Abstract: A non-destructive technique and related array for writing and reading magnetic memory cells, including sampling a first signal of a selected read line corresponding to select memory cells, applying a magnetic field to the select memory cells, sampling a second signal of the selected read line, and comparing the first and second signals to determine a logic state of the select memory cells.

Abstract translation: 一种用于写入和读取磁存储单元的非破坏性技术和相关阵列，包括对与选择存储器单元相对应的所选读取行的第一信号进行采样，向选择存储单元施加磁场，对所选择的读取的第二信号 并且比较第一和第二信号以确定选择存储器单元的逻辑状态。

公开(公告)号：US07042032B2

公开(公告)日：2006-05-09

申请号：US10401945

申请日：2003-03-27

Applicant: Wen-Chin Lin ,  Denny Duan-Lee Tang ,  Chao-Hsiung Wang

Inventor： Wen-Chin Lin ,  Denny Duan-Lee Tang ,  Chao-Hsiung Wang

IPC: H01L29/76

CPC classification number: H01L43/08 ,  G11C11/15 ,  H01L43/12

Abstract: A magnetoresistive magnetic data storage product and a method for fabrication thereof both employ a magnetic data storage device formed over a substrate. The magnetic data storage device comprises a free magnetoresistive material layer separated from a pinned magnetoresistive material layer by a dielectric spacer material layer, each having a sidewall. The magnetic data storage product also comprises a sidewall spacer material layer formed annularly surrounding and covering the sidewall of at least one of the free magnetoresistive material layer and the pinned magnetoresistive material layer. The magnetic data storage product is fabricated with enhanced magnetic data storage density.

Abstract translation: 磁阻磁数据存储产品及其制造方法都采用形成在衬底上的磁数据存储装置。 磁数据存储装置包括通过电介质间隔物材料层与固定磁阻材料层分离的自由磁阻材料层，每层具有侧壁。 磁数据存储产品还包括环形围绕并覆盖自由磁阻材料层和钉扎磁阻材料层中的至少一个的侧壁的侧壁间隔物材料层。 磁数据存储产品采用增强的磁数据存储密度制造。

公开(公告)号：US07035083B2

公开(公告)日：2006-04-25

申请号：US10804899

申请日：2004-03-19

Applicant: Wen-Chin Lin ,  Denny Tang ,  Li-Shyue Lai ,  Chung-Long Chang ,  Chun-Hon Chen

Inventor： Wen-Chin Lin ,  Denny Tang ,  Li-Shyue Lai ,  Chung-Long Chang ,  Chun-Hon Chen

IPC: H01G4/06

CPC classification number: H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor for use within a microelectronic product employs a first capacitor plate layer that includes a first series of horizontally separated and interconnected tines. A capacitor dielectric layer separates the first capacitor plate layer from a second capacitor plate layer. The second capacitor plate layer includes a second series of horizontally separated and interconnected tines horizontally interdigitated with the first series of horizontally separated and interconnected tines. The capacitor is formed employing a self-aligned method and the capacitor dielectric layer is formed in a serpentine shape.

Abstract translation: 在微电子产品中使用的电容器采用第一电容器板层，其包括第一系列水平分离和互连的尖齿。 电容器电介质层将第一电容器板层与第二电容器板层分开。 第二电容器板层包括与第一系列水平分离和互相联接的齿水平地交叉指向的第二系列水平分离和互连的齿。 使用自对准方法形成电容器，并且电容器介电层形成为蛇形形状。