公开(公告)号：US5564117A

公开(公告)日：1996-10-08

申请号：US468083

申请日：1995-06-06

申请人： Derek J. Lentz ,  Johannes Wang ,  Trevor Deosaran ,  Linley M. Young ,  Kian-Chin Yap ,  Le T. Nguyen ,  Makoto Matsubayashi ,  Te-Li Lau

发明人： Derek J. Lentz ,  Johannes Wang ,  Trevor Deosaran ,  Linley M. Young ,  Kian-Chin Yap ,  Le T. Nguyen ,  Makoto Matsubayashi ,  Te-Li Lau

IPC分类号： B41J5/30 ,  B41J29/38 ,  G06F3/12 ,  G06F9/308 ,  G06F15/78 ,  G06K15/00 ,  G06K15/02 ,  G06T1/20 ,  G06F15/16

CPC分类号： G06F9/30018 ,  G06K15/00 ,  G06K15/02 ,  G06K2215/0002 ,  G06K2215/0005 ,  G06K2215/004 ,  G06K2215/0054 ,  G06K2215/0062 ,  G06K2215/0071 ,  G06K2215/0082

摘要： A VLSIC page printer controller includes an instruction processor which responds to a host computer and a printer video processor for accessing data from memory under the control of the instruction processor and serializing data for transfer to a printer through a video port. An I/O interface interconnects the printer controller with an I/O bus to which is connected a host computer, memory devices, and other peripheral devices. An internal memory interface connects the printer controller to memory, and the printer video processor is provided with direct memory access (DMA). Data and instruction caches and an instruction ROM are provided on-chip. A RISC instruction processing unit includes as an integral part thereof the special function, circuits of orthogonal rotator, bit/byte mirror, and pixel modification.

摘要翻译： VLSIC页面打印机控制器包括指令处理器，其响应于主计算机和打印机视频处理器，用于在指令处理器的控制下从存储器访问数据，并串行化数据以通过视频端口传送到打印机。 I / O接口将打印机控制器与连接到主机，存储设备和其他外围设备的I / O总线互连。 内部存储器接口将打印机控制器连接到存储器，并且打印机视频处理器具有直接存储器访问（DMA）。 数据和指令高速缓存以及指令ROM片上提供。 RISC指令处理单元作为其整体部分包括特殊功能，正交旋转器的电路，位/字节镜和像素修改。

公开(公告)号：US5559951A

公开(公告)日：1996-09-24

申请号：US383015

申请日：1995-02-03

申请人： Derek J. Lentz ,  Johannes Wang ,  Trevor Deosaran ,  Linley M. Young ,  Kian-Chin Yap ,  Le Trong Nguyen ,  Makoto Matsubayashi ,  Te-Li Lau

发明人： Derek J. Lentz ,  Johannes Wang ,  Trevor Deosaran ,  Linley M. Young ,  Kian-Chin Yap ,  Le Trong Nguyen ,  Makoto Matsubayashi ,  Te-Li Lau

IPC分类号： B41J5/30 ,  B41J29/38 ,  G06F3/12 ,  G06F9/308 ,  G06F15/78 ,  G06K15/00 ,  G06K15/02 ,  G06T1/20 ,  G06F15/16

CPC分类号： G06F9/30018 ,  G06K15/00 ,  G06K15/02 ,  G06K2215/0002 ,  G06K2215/0005 ,  G06K2215/004 ,  G06K2215/0054 ,  G06K2215/0062 ,  G06K2215/0071 ,  G06K2215/0082

摘要： A VLSIC page printer controller includes an instruction processor which responds to a host computer and a printer video processor for accessing data from memory under the control of the instruction processor and serializing data for transfer to a printer through a video port. An I/0 interface interconnects the printer controller with an I/O bus to which is connected a host computer, memory devices, and other peripheral devices. An internal memory interface connects the printer controller to memory, and the printer video processor is provided with direct memory access (DMA). Data and instruction caches and an instruction ROM are provided on-chip. A RISC instruction processing unit includes as an integral part thereof the special function circuits of orthogonal rotator, bit/byte mirror, and pixel modification.

摘要翻译： VLSIC页面打印机控制器包括指令处理器，其响应于主计算机和打印机视频处理器，用于在指令处理器的控制下从存储器访问数据，并串行化数据以通过视频端口传送到打印机。 I / O接口将打印机控制器与连接到主机，存储设备和其他外围设备的I / O总线互连。 内部存储器接口将打印机控制器连接到存储器，并且打印机视频处理器具有直接存储器访问（DMA）。 数据和指令高速缓存以及指令ROM片上提供。 RISC指令处理单元作为其整体部分包括正交旋转器的特殊功能电路，位/字节镜和像素修改。

公开(公告)号：US5394515A

公开(公告)日：1995-02-28

申请号：US267646

申请日：1994-06-28

申请人： Derek J. Lentz ,  Johannes Wang ,  Trevor Deosaran ,  Linley M. Young ,  Kian-Chin Yap ,  Le Trong Nguyen ,  Makoto Matsubayashi ,  Te-Li Lau

发明人： Derek J. Lentz ,  Johannes Wang ,  Trevor Deosaran ,  Linley M. Young ,  Kian-Chin Yap ,  Le Trong Nguyen ,  Makoto Matsubayashi ,  Te-Li Lau

IPC分类号： B41J5/30 ,  B41J29/38 ,  G06F3/12 ,  G06F9/308 ,  G06F15/78 ,  G06K15/00 ,  G06K15/02 ,  G06T1/20 ,  G06F15/00

CPC分类号： G06F9/30018 ,  G06K15/00 ,  G06K15/02 ,  G06K2215/0002 ,  G06K2215/0005 ,  G06K2215/004 ,  G06K2215/0054 ,  G06K2215/0062 ,  G06K2215/0071 ,  G06K2215/0082

摘要： A VLSIC page printer controller includes an instruction processor which responds to a host computer and a printer video processor for accessing data from memory under the control of the instruction processor and serializing data for transfer to a printer through a video port. An I/O interface interconnects the printer controller with an I/O bus to which is connected a host computer, memory devices, and other peripheral devices. An internal memory interface connects the printer controller to memory, and the printer video processor is provided with direct memory access (DMA). Data and instruction caches and an instruction ROM are provided on-chip. A RISC instruction processing unit includes as an integral part thereof the special function circuits of orthogonal rotator, bit/byte mirror, and pixel modification.

摘要翻译： VLSIC页面打印机控制器包括指令处理器，其响应于主计算机和打印机视频处理器，用于在指令处理器的控制下从存储器访问数据，并串行化数据以通过视频端口传送到打印机。 I / O接口将打印机控制器与连接到主机，存储设备和其他外围设备的I / O总线互连。 内部存储器接口将打印机控制器连接到存储器，并且打印机视频处理器具有直接存储器访问（DMA）。 数据和指令高速缓存以及指令ROM片上提供。 RISC指令处理单元作为其整体部分包括正交旋转器的特殊功能电路，位/字节镜和像素修改。

公开(公告)号：US5539911A

公开(公告)日：1996-07-23

申请号：US817810

申请日：1992-01-08

申请人： Le T. Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le T. Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F9/42 ,  G06F13/00

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instruction sets and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers which are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

摘要翻译： 高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。 计算机系统获取和存储程序指令集。 每个指令集包括具有指定的顺序程序顺序（按顺序）的多个固定长度指令。 计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令集并且调度用于由功能单元执行无序执行的指令。 寄存器文件包括一组临时数据寄存器，由指令执行控制单元用来接收由功能单元产生的数据结果。 每个执行指令的数据结果被存储在临时数据寄存器中，直到所有先前的指令都被执行，从而按顺序退出执行的指令。

公开(公告)号：US07739482B2

公开(公告)日：2010-06-15

申请号：US11642599

申请日：2006-12-21

申请人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F15/76

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

公开(公告)号：US06256720B1

公开(公告)日：2001-07-03

申请号：US09436986

申请日：1999-11-09

申请人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F930

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

摘要翻译： 高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。 计算机系统以指定的顺序程序顺序（按顺序）获取多个固定长度指令。 计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令并调度用于由功能单元执行无序执行的指令。 寄存器文件包括一组由指令执行控制单元用于接收由功能单元产生的数据结果的临时数据寄存器。 每个执行指令的数据结果被存储在临时数据寄存器中，直到所有先前的指令都被执行，从而按顺序退出执行的指令。

公开(公告)号：US6038653A

公开(公告)日：2000-03-14

申请号：US158568

申请日：1998-09-22

申请人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38

CPC分类号： G06F9/30167 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30141 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3865 ,  G06F9/3885

摘要： The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across mutliple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.

摘要翻译： 高性能的基于RISC核心的微处理器架构包括用于从指令存储器取出指令集的指令获取单元和通过并行的功能单元阵列实现多个指令的并发执行的执行单元。 提取单元通常在指令缓冲器中保持预定数量的指令。 执行单元包括指令选择单元，耦合到指令缓冲器，用于选择用于执行的指令;以及多个功能单元，用于执行指令指定的功能操作。 在指令选择单元内的统一指令调度器，当确定可用于执行的指令并且实现必要的计算功能的功能单元中的至少一个可用时，通过功能单元启动对指令的处理。 在多个执行数据路径上执行统一调度，其中每个执行数据路径和相应的功能单元通常针对要对数据执行的计算函数类型进行优化：整数，浮点和布尔值。 在每个数据路径中以及数据路径之间提供的功能单元的数量，类型和计算细节是相互独立的。

公开(公告)号：US5961629A

公开(公告)日：1999-10-05

申请号：US150706

申请日：1998-09-10

申请人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/28

CPC分类号： G06F9/3855 ,  G06F9/30054 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

摘要翻译： 高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。 计算机系统以指定的顺序程序顺序（按顺序）获取多个固定长度指令。 计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令并调度用于由功能单元执行无序执行的指令。 寄存器文件包括一组由指令执行控制单元用于接收由功能单元产生的数据结果的临时数据寄存器。 每个执行指令的数据结果被存储在临时数据寄存器中，直到所有先前的指令都被执行，从而按顺序退出执行的指令。

公开(公告)号：US06959375B2

公开(公告)日：2005-10-25

申请号：US10282045

申请日：2002-10-29

申请人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F9/42 ,  G06F9/50 ,  G06F15/16

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

摘要翻译： 高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。 计算机系统以指定的顺序程序顺序（按顺序）获取多个固定长度指令。 计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令并调度用于由功能单元执行无序执行的指令。 寄存器文件包括一组由指令执行控制单元用于接收由功能单元产生的数据结果的临时数据寄存器。 每个执行指令的数据结果存储在临时数据寄存器中，直到执行所有先前的指令为止，从而按顺序退出执行的指令。

公开(公告)号：US06941447B2

公开(公告)日：2005-09-06

申请号：US10700520

申请日：2003-11-05

申请人： Le-Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

发明人： Le-Trong Nguyen ,  Derek J. Lentz ,  Yoshiyuki Miyayama ,  Sanjiv Garg ,  Yasuaki Hagiwara ,  Johannes Wang ,  Te-Li Lau ,  Sze-Shun Wang ,  Quang H. Trang

IPC分类号： G06F9/32 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F9/42 ,  G06F13/40

CPC分类号： G06F9/3822 ,  G06F9/30061 ,  G06F9/30072 ,  G06F9/30112 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30167 ,  G06F9/327 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/3885

摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.