-
公开(公告)号：US08860141B2
公开(公告)日：2014-10-14
申请号：US13345439
申请日：2012-01-06
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
IPC分类号： H01L21/70
CPC分类号： H01L27/1104 , G11C5/025 , H01L21/28123 , H01L27/0207
摘要： A semiconductor chip has shapes on a particular level that are small enough to require a first mask and a second mask, the first mask and the second mask used in separate exposures during processing. A circuit on the semiconductor chip requires close tracking between a first and a second FET (field effect transistor). For example, the particular level may be a gate shape level. Separate exposures of gate shapes using the first mask and the second mask will result in poorer FET tracking (e.g., gate length, threshold voltage) than for FETs having gate shapes defined by only the first mask. FET tracking is selectively improved by laying out a circuit such that selective FETs are defined by the first mask. In particular, static random access memory (SRAM) design benefits from close tracking of six or more FETs in an SRAM cell.
摘要翻译： 半导体芯片具有在足够小以至要求第一掩模和第二掩模的特定等级上的形状，第一掩模和第二掩模在处理期间分开曝光中使用。 半导体芯片上的电路需要在第一和第二FET（场效应晶体管）之间的紧密跟踪。 例如，特定级别可以是门形状级别。 使用第一掩模和第二掩模的栅极形状的单独曝光将导致比仅由第一掩模限定的栅极形状的FET更差的FET跟踪（例如，栅极长度，阈值电压）。 通过布置电路来选择性地提高FET跟踪，使得选择性FET由第一掩模限定。 特别地，静态随机存取存储器（SRAM）设计受益于在SRAM单元中紧密跟踪六个或更多个FET。
-
2.发明申请DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO CLEAR DATA AT POWER-UP 有权动态随机存取存储器的数据安全使用身体偏差清除数据上电公开(公告)号：US20120087176A1
公开(公告)日：2012-04-12
申请号：US12898924
申请日：2010-10-06
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
CPC分类号： G11C7/24 , G11C5/145 , G11C7/20 , G11C11/4072 , G11C11/4078
摘要： A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.
摘要翻译： 电路和方法在上电时擦除存储在DRAM芯片中的所有数据，以提高数据安全性。 通过增加单元的体电压同时接通DRAM存储单元的晶体管，可以擦除所有的DRAM存储单元。 在示例电路中，通过由对存储器单元的p阱施加电压的上电复位（POR）信号控制的电荷泵增加体电压。 向p阱施加的电压降低了电池的阈值电压，使得存储器单元的NFET晶体管将导通。 当所有设备都打开时，存储在存储单元中的数据将被擦除，因为连接到通用位线的所有单元的电压合并为单个值。
-
3.发明授权Data security for dynamic random access memory using body bias to clear data at power-up 有权使用身体偏倚的动态随机存取存储器的数据安全性，以在上电时清除数据公开(公告)号：US08467230B2
公开(公告)日：2013-06-18
申请号：US12898924
申请日：2010-10-06
申请人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
发明人： Derick Gardner Behrends , Todd Alan Christensen , Travis Reynold Hebig , Michael Launsbach , Daniel Mark Nelson
IPC分类号： G11C11/24
CPC分类号： G11C7/24 , G11C5/145 , G11C7/20 , G11C11/4072 , G11C11/4078
摘要： A circuit and method erase at power-up all data stored in a DRAM chip for increased data security. All the DRAM memory cells are erased by turning on the transistors for the DRAM storage cells simultaneously by increasing the body voltage of cells. In the example circuit, the body voltage is increased by a charge pump controlled by a power-on-reset (POR) signal applying a voltage to the p-well of the memory cells. The added voltage to the p-well lowers the threshold voltage of the cell, such that the NFET transistor of the memory cell will turn on. With all the devices turned on, the data stored in the memory cells is erased as the voltage of all the cells connected to a common bitline coalesce to a single value.
摘要翻译： 电路和方法在上电时擦除存储在DRAM芯片中的所有数据，以提高数据安全性。 通过增加单元的体电压同时接通DRAM存储单元的晶体管，可以擦除所有的DRAM存储单元。 在示例电路中，通过由对存储器单元的p阱施加电压的上电复位（POR）信号控制的电荷泵增加体电压。 向p阱施加的电压降低了电池的阈值电压，使得存储器单元的NFET晶体管将导通。 当所有设备都打开时，存储在存储单元中的数据将被擦除，因为连接到通用位线的所有单元的电压合并为单个值。
-
4.发明授权Delay chain burn-in for increased repeatability of physically unclonable functions 失效延迟链老化可增加物理不可克隆功能的重复性公开(公告)号：US08159260B1
公开(公告)日：2012-04-17
申请号：US12898044
申请日：2010-10-05
CPC分类号： G06F7/588 , H04L9/0866
摘要： A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.
摘要翻译： 电路和方法通过在芯片烧录期间通过两个延迟链增强信号延迟的变化来增加物理上不可检测的功能（PUF）的重复性。 老化电路在老化过程中将两个延迟链的输入保持相反的随机值。 延迟链中所有在输入端具有低电平值的PFET将以更高的导通电压进行烧录。 由于在两个延迟链中受影响的PFET在老化期间被相反的转变驱动，所以两个延迟链中的延迟组件的交替组合受老化周期的影响。 在正常操作下，两个延迟链看到相同的输入，所以只有一个链延迟增加，以实现两个延迟路径的统计上可靠的差异，从而增加了PUF电路的整体重复性。
-
5.发明申请DELAY CHAIN BURN-IN FOR INCREASED REPEATABILITY OF PHYSICALLY UNCLONABLE FUNCTIONS 失效延迟链燃烧以增加物理不可靠功能的重复性公开(公告)号：US20120081143A1
公开(公告)日：2012-04-05
申请号：US12898044
申请日：2010-10-05
IPC分类号： H03K19/00
CPC分类号： G06F7/588 , H04L9/0866
摘要： A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.
摘要翻译： 电路和方法通过在芯片烧录期间通过两个延迟链增强信号延迟的变化来增加物理上不可检测的功能（PUF）的重复性。 老化电路在老化过程中将两个延迟链的输入保持相反的随机值。 延迟链中所有在输入端具有低电平值的PFET将以更高的导通电压进行烧录。 由于在两个延迟链中受影响的PFET在老化期间被相反的转变驱动，所以两个延迟链中的延迟组件的交替组合受老化周期的影响。 在正常操作下，两个延迟链看到相同的输入，所以只有一个链延迟增加，以实现两个延迟路径的统计上可靠的差异，从而增加了PUF电路的整体重复性。
-
公开(公告)号：US20100214859A1
公开(公告)日：2010-08-26
申请号：US12389420
申请日：2009-02-20
CPC分类号： G11C11/413 , G11C8/08
摘要： A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor.
摘要翻译： 一种用于在存储器中实现升压的字线电压的方法和字线电压升压电路，以及设置有该电路所在的设计结构。 字线升压电路接收预充电信号，使用耦合到自举电容器的开关晶体管，并响应于预充电信号产生升压电压电平。 提升的电压电平被施加到字线驱动器的输出级的电压源，导致所选字线的字线电压电平升高。 开关晶体管由预充电信号控制，并且提供升压电压电平的自举电容的节点由开关晶体管驱动为高电平。
-
公开(公告)号：US07924633B2
公开(公告)日：2011-04-12
申请号：US12389420
申请日：2009-02-20
IPC分类号： G11C7/00
CPC分类号： G11C11/413 , G11C8/08
摘要： A method and wordline voltage boosting circuit for implementing boosted wordline voltage in memories, and a design structure on which the subject circuit resides are provided. The wordline voltage boosting circuit receives a precharge signal, uses a switching transistor coupled to a bootstrap capacitor, and generates a boosted voltage level responsive to the precharge signal. The boosted voltage level is applied to a voltage supply of an output stage of a wordline driver, causing the wordline voltage level of a selected wordline to be boosted. The switching transistor is controlled by the precharge signal and a node of the bootstrap capacitor supplying the boosted voltage level is driven high by the switching transistor.
摘要翻译： 一种用于在存储器中实现升压的字线电压的方法和字线电压升压电路，以及设置有该电路所在的设计结构。 字线升压电路接收预充电信号，使用耦合到自举电容器的开关晶体管，并响应于预充电信号产生升压电压电平。 提升的电压电平被施加到字线驱动器的输出级的电压源，导致所选字线的字线电压电平升高。 开关晶体管由预充电信号控制，并且提供升压电压电平的自举电容的节点由开关晶体管驱动为高电平。
-
8.发明申请Method for Implementing Level Shifter Circuits and Low Power Level Shifter Circuits for Integrated Circuits 失效实现电平移位器电路的方法和用于集成电路的低功率电平移位器电路公开(公告)号：US20080084237A1
公开(公告)日：2008-04-10
申请号：US11538967
申请日：2006-10-05
IPC分类号： H03L5/00
CPC分类号： H03K19/094 , H03K19/018521
摘要： A low power level shifter circuit includes an input inverter operating in a domain of a first voltage supply. The input inverter receives an input signal and provides a first inverted signal. An output inverter operating in a domain of a second voltage supply coupled to the input inverter and provides an output signal having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second voltage supply is higher than the first voltage supply. A leakage current control circuit includes a finisher transistor connected between the second voltage supply and the input to the output inverter and a path control transistor control a path between the first voltage supply and the input inverter.
摘要翻译： 低功率电平移位器电路包括在第一电压源的域中操作的输入反相器。 输入反相器接收输入信号并提供第一反相信号。 输出反相器，其在与输入反相器耦合的第二电压源的区域中工作，并提供具有与第二电压源相对应的电压电平的输出信号和对应于输入信号的逻辑值。 第二电压源高于第一电压源。 泄漏电流控制电路包括连接在第二电压源和输出反相器的输入端之间的整流晶体管，并且路径控制晶体管控制第一电压源与输入反相器之间的路径。
-
9.发明申请Method for Implementing Level Shifter Circuits and Low Power Level Shifter Circuits for Integrated Circuits 审中-公开实现电平移位器电路的方法和用于集成电路的低功率电平移位器电路公开(公告)号：US20080084231A1
公开(公告)日：2008-04-10
申请号：US11867108
申请日：2007-10-04
IPC分类号： H03K19/094
CPC分类号： H03K19/018521 , H03K19/094
摘要： A low power level shifter circuit for integrated circuits, and a design structure on which the subject circuit resides are provided. The low power level shifter circuit includes an input inverter operating in a domain of a first voltage supply. The input inverter receives an input signal and provides a first inverted signal. An output inverter operating in a domain of a second voltage supply coupled to the input inverter and provides an output signal having a voltage level corresponding to the second voltage supply and a logic value corresponding to the input signal. The second voltage supply is higher than the first voltage supply. A leakage current control circuit includes a finisher transistor connected between the second voltage supply and the input to the output inverter and a path control transistor control a path between the first voltage supply and the input inverter.
摘要翻译： 用于集成电路的低功率电平移位器电路，以及设置有被摄体电路的设计结构。 低功率电平移位器电路包括在第一电压源的域中操作的输入反相器。 输入反相器接收输入信号并提供第一反相信号。 输出反相器，其在与输入反相器耦合的第二电压源的区域中工作，并提供具有与第二电压源相对应的电压电平的输出信号和对应于输入信号的逻辑值。 第二电压源高于第一电压源。 泄漏电流控制电路包括连接在第二电压源和输出反相器的输入端之间的整流晶体管，并且路径控制晶体管控制第一电压源与输入反相器之间的路径。
-
10.发明申请IMPLEMENTING LOW POWER LEVEL SHIFTER FOR HIGH PERFORMANCE INTEGRATED CIRCUITS 审中-公开实现高性能集成电路的低功率电平变换器公开(公告)号：US20090174457A1
公开(公告)日：2009-07-09
申请号：US11970624
申请日：2008-01-08
IPC分类号： H03L5/00
CPC分类号： H03K3/356165 , H03K3/012
摘要： A low power level shifter circuit for high performance integrated circuits includes an input inverter operating in a domain of a first voltage supply and receiving an input signal and a design structure on which the subject circuit resides is provided. An output stage operating in a domain of a higher second voltage supply includes a first output inverter connected to the input inverter and a second output inverter connected in series with the first output inverter. The second output inverter provides a level shifted output signal having a voltage level corresponding to the second voltage supply. A series connected finisher transistor and finisher control transistor are connected between the second voltage supply and an input to the first output inverter. The finisher control transistor is activated responsive to the input signal. A path control transistor controls a path between the first voltage supply and the input inverter. The path control transistor being activated responsive to the level shifted output signal.
摘要翻译： 用于高性能集成电路的低功率电平移位器电路包括在第一电压源的区域中操作并接收输入信号的输入反相器和设置有被摄体电路的设计结构。 在较高的第二电压源的区域中工作的输出级包括连接到输入反相器的第一输出反相器和与第一输出反相器串联连接的第二输出反相器。 第二输出反相器提供具有对应于第二电压源的电压电平的电平移位输出信号。 串联连接的整流晶体管和整流器控制晶体管连接在第二电压源和与第一输出反相器的输入端之间。 整理器控制晶体管响应于输入信号被激活。 路径控制晶体管控制第一电压源和输入反相器之间的路径。 路径控制晶体管响应于电平移位的输出信号被激活。
-
-
-
-
-
-
-
-
-
搜索结果
79 条记录 (耗时 0.024 秒)
