公开(公告)号：US20130271155A1

公开(公告)日：2013-10-17

申请号：US13626434

申请日：2012-09-25

申请人： Dermot O'Keeffe ,  Donal Bourke ,  David Harty ,  Tudor Vinereanu ,  Colin Lyden

发明人： Dermot O'Keeffe ,  Donal Bourke ,  David Harty ,  Tudor Vinereanu ,  Colin Lyden

IPC分类号： G01R27/02

CPC分类号： G01R27/28

摘要： A digital sine wave may be converted to an analog signal at a digital to analog converter (DAC). The converted analog signal may be supplied to a device and an analog return signal from the device may be passed through a relaxed anti-aliasing filter and converted to digital code words at an analog to digital converter (ADC). An impedance may be calculated from the results of a Fourier analysis of the digital code words. The ADC and DAC clock frequencies may be asynchronous, independently variable, and have a greatest common factor of 1. The clock frequencies of the ADC and/or DAC may be adjusted to change a location of images in the ADC spectrum. By using these different, adjustable clock frequencies for the ADC and the DAC, an analog signal may have increased aliasing without introducing signal errors at a frequency of interest.

摘要翻译： 数字正弦波可以在数模转换器（DAC）转换为模拟信号。 转换的模拟信号可以被提供给设备，并且来自设备的模拟返回信号可以通过松弛的抗混叠滤波器并且在模数转换器（ADC）处被转换成数字码字。 可以根据数字码字的傅立叶分析的结果来计算阻抗。 ADC和DAC时钟频率可以是异步的，可独立变化的，并且具有最大的共同因子1. ADC和/或DAC的时钟频率可以被调整以改变ADC频谱中图像的位置。 通过为ADC和DAC使用这些不同的可调时钟频率，模拟信号可能会增加混叠，而不会在感兴趣的频率下引入信号错误。

公开(公告)号：US08823465B2

公开(公告)日：2014-09-02

申请号：US13469914

申请日：2012-05-11

申请人： Donal Bourke ,  Dermot O'Keeffe

发明人： Donal Bourke ,  Dermot O'Keeffe

IPC分类号： H03B5/30 ,  H03K3/011 ,  H03K3/012 ,  H03K3/013

CPC分类号： H03K3/011 ,  H03B5/364 ,  H03B2202/05 ,  H03K3/012 ,  H03K3/013

摘要： A clock generator is disclosed for use with an oscillator device. The clock generator may include a signal conditioning pre-filter and a comparator. The signal conditioner may have an input for a signal from the oscillator device, and may include a high pass filter component and a low pass filter component. The high pass filter component may pass amplitude and frequency components of the input oscillator signal but reject a common mode component of the oscillator signal. Instead, the high pass filter component further may generate its own common mode component locally over which the high frequency components are superimposed. The low pass filter component may generate a second output signal that represents the locally-generated common mode component of the first output signal. The clock generator may have a comparator as an input stage which is coupled to first and second outputs of the filter structure.

摘要翻译： 公开了与振荡器装置一起使用的时钟发生器。 时钟发生器可以包括信号调节预滤波器和比较器。 信号调节器可以具有来自振荡器装置的信号的输入，并且可以包括高通滤波器部件和低通滤波器部件。 高通滤波器分量可以传递输入振荡器信号的振幅和频率分量，但是抑制振荡器信号的共模分量。 相反，高通滤波器分量还可以在本地产生其自身的共模分量，在该共模分量上叠加高频分量。 低通滤波器分量可以产生表示第一输出信号的局部产生的共模分量的第二输出信号。 时钟发生器可以具有比较器作为输入级，其耦合到滤波器结构的第一和第二输出。

公开(公告)号：US08659349B1

公开(公告)日：2014-02-25

申请号：US13626630

申请日：2012-09-25

申请人： Colin Lyden ,  Donal Bourke ,  Dennis A. Dempsey ,  Dermot G. O'Keeffe ,  Patrick Kirby

发明人： Colin Lyden ,  Donal Bourke ,  Dennis A. Dempsey ,  Dermot G. O'Keeffe ,  Patrick Kirby

IPC分类号： G06G7/12

CPC分类号： G01N27/028 ,  G01N27/3273 ,  G01N27/49 ,  H03F1/34 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2200/462 ,  H03L5/00

摘要： A control circuit for use with a four terminal sensor, the sensor having first and second drive terminals and first and second measurement terminals, the control circuit arranged to drive at least one of the first and second drive terminals with an excitation signal, to sense a voltage difference between the first and second measurement terminals, and control the excitation signal such that the voltage difference between the first and second measurement terminals is within a target range of voltages, and wherein the control circuit includes N poles in its transfer characteristic and N−1 zeros in its transfer characteristic such that when a loop gain falls to unity the phase shift around a closed loop is not substantially 2π radians or a multiple thereof, where N is greater than 1.

摘要翻译： 一种与四端子传感器一起使用的控制电路，所述传感器具有第一和第二驱动端子以及第一和第二测量端子，所述控制电路被布置成用激励信号驱动第一和第二驱动端子中的至少一个，以感测 并且控制所述激励信号，使得所述第一测量端子与所述第二测量端子之间的电压差在目标电压范围内，并且其中所述控制电路在其传输特性中包括N极，并且所述N- 1的零传递特性使得当环路增益下降到1时，围绕闭环的相移基本上不是2pi弧度或其倍数，其中N大于1。

公开(公告)号：US20070262893A1

公开(公告)日：2007-11-15

申请号：US11434329

申请日：2006-05-15

申请人： Chin Li ,  Donal Bourke ,  Steven Steckler ,  Eoin Carey

发明人： Chin Li ,  Donal Bourke ,  Steven Steckler ,  Eoin Carey

IPC分类号： H03M1/66

CPC分类号： H03M1/1061 ,  H03F2200/504 ,  H03M1/745

摘要： Various techniques for biasing a radio frequency digital-to-analog converter are described. In one embodiment, a baseband processor may comprise a plurality of output drivers to generate a plurality of base currents for biasing a radio frequency digital-to-analog converter. The baseband processor may comprise a serial control interface to generate a programming signal for controlling a relationship among the plurality of base currents. Other embodiments are described and claimed.

摘要翻译： 描述了用于偏置射频数模转换器的各种技术。 在一个实施例中，基带处理器可以包括多个输出驱动器，以产生用于偏置射频数模转换器的多个基极电流。 基带处理器可以包括串行控制接口以产生用于控制多个基极电流之间的关系的编程信号。 描述和要求保护其他实施例。

公开(公告)号：US07317412B2

公开(公告)日：2008-01-08

申请号：US11434329

申请日：2006-05-15

申请人： Chin Li ,  Donal Bourke ,  Steven Steckler ,  Eoin Carey

发明人： Chin Li ,  Donal Bourke ,  Steven Steckler ,  Eoin Carey

IPC分类号： H03M1/66

CPC分类号： H03M1/1061 ,  H03F2200/504 ,  H03M1/745

摘要： Various techniques for biasing a radio frequency digital-to-analog converter are described. In one embodiment, a baseband processor may comprise a plurality of output drivers to generate a plurality of base currents for biasing a radio frequency digital-to-analog converter. The baseband processor may comprise a serial control interface to generate a programming signal for controlling a relationship among the plurality of base currents. Other embodiments are described and claimed.

摘要翻译： 描述了用于偏置射频数模转换器的各种技术。 在一个实施例中，基带处理器可以包括多个输出驱动器，以产生用于偏置射频数模转换器的多个基极电流。 基带处理器可以包括串行控制接口以产生用于控制多个基极电流之间的关系的编程信号。 描述和要求保护其他实施例。

公开(公告)号：US20090027112A1

公开(公告)日：2009-01-29

申请号：US11828419

申请日：2007-07-26

申请人： Chin Li ,  Donal Bourke ,  Joseph G. DeCarlo

发明人： Chin Li ,  Donal Bourke ,  Joseph G. DeCarlo

IPC分类号： G05F3/02

CPC分类号： H03F3/45179 ,  H03F1/3211 ,  H03F2200/453 ,  H03F2203/45288 ,  H03F2203/45356 ,  H03F2203/45511

摘要： Techniques for providing precise transconductance values are disclosed. For instance, an apparatus includes a slave transconductance cell and a control loop. The control loop provides a tuning voltage to the slave transconductance cell. Moreover, the control loop includes a master transconductance cell that generates a master output current, and a current amplifier that generates the tuning voltage based on an error signal. The error signal reflects a difference between a reference current and the master output current. Further, the current amplifier provides the tuning voltage to the master transconductance cell.

摘要翻译： 公开了提供精确跨导值的技术。 例如，一种装置包括从跨系统单元和控制回路。 控制回路向从属跨导单元提供调谐电压。 此外，控制回路包括产生主输出电流的主跨导单元和基于误差信号产生调谐电压的电流放大器。 误差信号反映了参考电流和主输出电流之间的差异。 此外，电流放大器将调谐电压提供给主跨导单元。