摘要:
This disclosure relates to adjusting a limit cycle frequency of a pulse width modulation in an analog to digital converter as a function of an input signal level to increase dynamic range.
摘要:
This disclosure relates to adjusting a limit cycle frequency of a pulse width modulation in an analog to digital converter as a function of an input signal level to increase dynamic range.
摘要:
Disclosed are techniques for reducing noise and providing conversion signals in electronic components, including pulse width modulation (PWM) oversampling converters, by performing signal conversion having finite impulse response (FIR) feedback. Implementations may reduce the sensitivity of the conversion process to jitter in the sampling clock, thereby reducing noise and providing conversion signals.
摘要:
Disclosed are techniques for reducing noise and providing conversion signals in electronic components, including pulse width modulation (PWM) oversampling converters, by performing signal conversion having finite impulse response (FIR) feedback. Implementations may reduce the sensitivity of the conversion process to jitter in the sampling clock, thereby reducing noise and providing conversion signals.
摘要:
Clock signal jitter detection circuit for detecting a clock signal jitter in a reference clock signal (CLK), having a switched-capacitor reference digital-analogue converter (15) which is clocked by the reference clock signal (CLK) and which converts a digital input signal into a first current, a current-controlled digital-analogue converter (16) which is clocked by the reference clock signal (CLK) and which converts the digital input signal into a second current, and having a current integrator (18) which integrates the difference between the first current and the second current to produce a signal which indicates the clock signal jitter in the reference clock signal (CLK).