Reference circuit for providing precision voltage and precision current
    1.
    发明授权
    Reference circuit for providing precision voltage and precision current 有权
    用于提供精密电压和精密电流的参考电路

    公开(公告)号:US07880534B2

    公开(公告)日:2011-02-01

    申请号:US12437699

    申请日:2009-05-08

    IPC分类号: G05F1/56 G05F3/26

    CPC分类号: G05F3/30

    摘要: A reference circuit for providing a precision voltage and a precision current includes a bandgap voltage reference circuit, a positive temperature coefficient calibrating circuit, a threshold voltage superposing circuit and precision current generator interconnected in cascade. From the bandgap voltage reference circuit, a bandgap voltage is outputted as the precision voltage, and a PTAT current is outputted to the positive temperature coefficient calibrating circuit along with the bandgap voltage for generating a PTAT voltage. In response to the PTAT voltage from the positive temperature coefficient calibrating circuit, the threshold voltage superposing circuit generates a first voltage which is equal to the PTAT voltage plus a threshold voltage. Then the precision current generator outputs a reference current as the precision current in response to the first voltage.

    摘要翻译: 用于提供精密电压和精密电流的参考电路包括级联的带隙电压参考电路,正温度系数校准电路,阈值电压叠加电路和精密电流发生器。 从带隙电压基准电路中,输出带隙电压作为精密电压,并且将PTAT电流与产生PTAT电压的带隙电压一起输出到正温度系数校准电路。 响应于来自正温度系数校准电路的PTAT电压,阈值电压叠加电路产生等于PTAT电压加上阈值电压的第一电压。 然后,精密电流发生器响应于第一电压输出参考电流作为精密电流。

    REFERENCE CIRCUIT FOR PROVIDING PRECISION VOLTAGE AND PRECISION CURRENT
    2.
    发明申请
    REFERENCE CIRCUIT FOR PROVIDING PRECISION VOLTAGE AND PRECISION CURRENT 有权
    提供精度电压和精度电流的参考电路

    公开(公告)号:US20100060345A1

    公开(公告)日:2010-03-11

    申请号:US12437699

    申请日:2009-05-08

    IPC分类号: G05F3/02

    CPC分类号: G05F3/30

    摘要: A reference circuit for providing a precision voltage and a precision current includes a bandgap voltage reference circuit, a positive temperature coefficient calibrating circuit, a threshold voltage superposing circuit and precision current generator interconnected in cascade. From the bandgap voltage reference circuit, a bandgap voltage is outputted as the precision voltage, and a PTAT current is outputted to the positive temperature coefficient calibrating circuit along with the bandgap voltage for generating a PTAT voltage. In response to the PTAT voltage from the positive temperature coefficient calibrating circuit, the threshold voltage superposing circuit generates a first voltage which is equal to the PTAT voltage plus a threshold voltage. Then the precision current generator outputs a reference current as the precision current in response to the first voltage.

    摘要翻译: 用于提供精密电压和精密电流的参考电路包括级联的带隙电压参考电路,正温度系数校准电路,阈值电压叠加电路和精密电流发生器。 从带隙电压基准电路中,输出带隙电压作为精密电压,并且将PTAT电流与产生PTAT电压的带隙电压一起输出到正温度系数校准电路。 响应于来自正温度系数校准电路的PTAT电压,阈值电压叠加电路产生等于PTAT电压加上阈值电压的第一电压。 然后,精密电流发生器响应于第一电压输出参考电流作为精密电流。

    Reference current generator circuit for low-voltage applications
    3.
    发明授权
    Reference current generator circuit for low-voltage applications 有权
    用于低压应用的参考电流发生器电路

    公开(公告)号:US07944194B2

    公开(公告)日:2011-05-17

    申请号:US12325777

    申请日:2008-12-01

    IPC分类号: G05F3/16

    CPC分类号: G05F1/561 G05F3/262

    摘要: A reference current generator circuit suitable for low-voltage applications is provided. The generator circuit is fabricated in a chip for generating a precise reference current based on a precise reference voltage and a precise external resistor. The generator circuit provides an equivalent resistance coupled in parallel with the external resistor to provide resistance compensation and reduce the impedance of seeing into the chip from a chip pad. In addition to the resistance compensation, only moderate capacitance compensation is required to enhance the phase margin of the generator circuit, so as to achieve a stable loop. Therefore, chip area and cost can be reduced in low-voltage applications. In addition, the generator circuit reproduces the reference current generated by the external resistor by utilizing current mirrors, so as to eliminate the effect on currents caused by parallel coupling of the equivalent resistance and the external resistor.

    摘要翻译: 提供了适用于低电压应用的参考电流发生器电路。 发生器电路制造在芯片中,用于基于精确的参考电压和精确的外部电阻器产生精确的参考电流。 发生器电路提供与外部电阻并联耦合的等效电阻,以提供电阻补偿并减少从芯片焊盘看到芯片的阻抗。 除电阻补偿之外,只需要适度的电容补偿来增强发电机电路的相位裕度,从而实现稳定的回路。 因此,在低电压应用中,芯片面积和成本可以降低。 此外,发电机电路通过利用电流镜来再现由外部电阻器产生的参考电流,从而消除由等效电阻和外部电阻器并联耦合引起的电流的影响。

    REFERENCE CURRENT GENERATOR CIRCUIT FOR LOW-VOLTAGE APPLICATIONS
    4.
    发明申请
    REFERENCE CURRENT GENERATOR CIRCUIT FOR LOW-VOLTAGE APPLICATIONS 有权
    用于低电压应用的参考电流发生器电路

    公开(公告)号:US20100052645A1

    公开(公告)日:2010-03-04

    申请号:US12325777

    申请日:2008-12-01

    IPC分类号: G05F3/16 G05F3/04

    CPC分类号: G05F1/561 G05F3/262

    摘要: A reference current generator circuit suitable for low-voltage applications is provided. The generator circuit is fabricated in a chip for generating a precise reference current based on a precise reference voltage and a precise external resistor. The generator circuit provides an equivalent resistance coupled in parallel with the external resistor to provide resistance compensation and reduce the impedance of seeing into the chip from a chip pad. In addition to the resistance compensation, only moderate capacitance compensation is required to enhance the phase margin of the generator circuit, so as to achieve a stable loop. Therefore, chip area and cost can be reduced in low-voltage applications. In addition, the generator circuit reproduces the reference current generated by the external resistor by utilizing current mirrors, so as to eliminate the effect on currents caused by parallel coupling of the equivalent resistance and the external resistor.

    摘要翻译: 提供了适用于低电压应用的参考电流发生器电路。 发生器电路制造在芯片中,用于基于精确的参考电压和精确的外部电阻器产生精确的参考电流。 发生器电路提供与外部电阻并联耦合的等效电阻,以提供电阻补偿并减少从芯片焊盘看到芯片的阻抗。 除电阻补偿之外,只需要适度的电容补偿来增强发电机电路的相位裕度,从而实现稳定的回路。 因此,在低电压应用中,芯片面积和成本可以降低。 此外,发电机电路通过利用电流镜来再现由外部电阻器产生的参考电流,从而消除由等效电阻和外部电阻器并联耦合引起的电流的影响。

    Deglitch circuit
    5.
    发明授权
    Deglitch circuit 有权
    Deglitch电路

    公开(公告)号:US07830181B1

    公开(公告)日:2010-11-09

    申请号:US12555181

    申请日:2009-09-08

    IPC分类号: H03K5/00

    CPC分类号: H03K5/1252

    摘要: A deglitch circuit including signal transmission units is provided. The signal transmission units are connected in serial to form a signal transmission unit string, and a first signal transmission unit of the signal transmission unit string receives a digital signal. Each signal transmission unit includes a first switch, a first delay circuit and a second switch. First and second terminals of the first switch are coupled to a previous signal transmission unit of the signal transmission unit string and an input terminal of the first delay circuit, respectively. The second switch is coupled between an output terminal of the first delay circuit and a first voltage. When the digital signal has a first logic state, the first switch is turned off, and the second switch is turned on. When the digital signal has a second logic state, the first switch is turned on, and the second switch is turned off.

    摘要翻译: 提供了包括信号传输单元的去电泳电路。 信号发送单元串联连接形成信号发送单元串,信号发送单元串的第一信号发送单元接收数字信号。 每个信号传输单元包括第一开关,第一延迟电路和第二开关。 第一开关的第一和第二端子分别耦合到信号传输单元串的先前信号传输单元和第一延迟电路的输入端。 第二开关耦合在第一延迟电路的输出端和第一电压之间。 当数字信号具有第一逻辑状态时,第一开关被关闭,并且第二开关被接通。 当数字信号具有第二逻辑状态时,第一开关接通,第二开关断开。

    Light-emitting device
    6.
    发明授权

    公开(公告)号:US11670668B2

    公开(公告)日:2023-06-06

    申请号:US17199445

    申请日:2021-03-12

    IPC分类号: H01L27/15 H01L33/56 H01L33/54

    摘要: A light-emitting device including a substrate, an insulating layer, an inner circuit structure, a plurality of light-emitting elements, an insulating encapsulation layer, and a transparent conductive layer is provided. The insulating layer is disposed on the substrate. The inner circuit structure is disposed on the insulating layer. The light-emitting elements are correspondingly disposed on the inner circuit structure. The insulating encapsulation layer is disposed on the inner circuit structure. The insulating encapsulating layer covers a portion of the inner circuit structure and encapsulates the light-emitting elements. The transparent conductive layer is disposed on the insulating encapsulating layer. The transparent conductive layer electrically connects the light-emitting elements, and serially connects the light-emitting elements.

    ORGANIC LIGHT EMITTING DISPLAY DEVICE
    8.
    发明申请

    公开(公告)号:US20200266377A1

    公开(公告)日:2020-08-20

    申请号:US16794255

    申请日:2020-02-19

    IPC分类号: H01L51/50 H01L51/52

    摘要: An organic light emitting display device including a substrate, an anode, a hole transport layer, a cathode, an electron transport layer and an organic light emitting layer is provided. The anode is located on the substrate. The hole transport layer is located on the anode. The cathode is located on the substrate. The electron transport layer is located on the cathode. The organic light emitting layer is located between the hole transport layer and the electron transport layer. A vertical projection of the anode on the substrate is not overlapped with a vertical projection of the cathode on the substrate.

    APPARATUS AND METHOD FOR FREQUENCY LOCKING
    9.
    发明申请
    APPARATUS AND METHOD FOR FREQUENCY LOCKING 有权
    用于频率锁定的装置和方法

    公开(公告)号:US20150131766A1

    公开(公告)日:2015-05-14

    申请号:US14135593

    申请日:2013-12-20

    IPC分类号: H04J3/06 H04L7/033

    CPC分类号: H04L7/033 H03L7/087 H04L7/005

    摘要: An apparatus and a method for frequency locking are provided. The apparatus includes a phase-locked loop (PLL), a local clock generator, a data buffer unit and a control unit. The PLL locks the phase and the frequency of a radio frequency signal to generate a recovery clock signal and received data. The data buffer unit writes the received data into an elastic buffer of the data buffer unit according to the frequency of the recovery clock signal, and reads the received data from the elastic buffer according to the frequency of a local clock signal generated by the local clock generator. The control unit obtains a write-in address and a read-out address in the elastic buffer, and sends a control signal to the local clock generator for adjusting the frequency of the local clock signal according to relationship between the write-in address and the read-out address.

    摘要翻译: 提供一种用于频率锁定的装置和方法。 该装置包括锁相环(PLL),本地时钟发生器,数据缓冲器单元和控制单元。 PLL锁定射频信号的相位和频率以产生恢复时钟信号和接收的数据。 数据缓冲器单元根据恢复时钟信号的频率将接收到的数据写入数据缓冲器单元的弹性缓冲器,并根据由本地时钟产生的本地时钟信号的频率从弹性缓冲器读取接收的数据 发电机。 控制单元在弹性缓冲器中获得写入地址和读出地址,并且根据写入地址和写入地址之间的关系向本地时钟发生器发送控制信号以调整本地时钟信号的频率 读出地址。

    Semiconductor devices with strained source/drain structures
    10.
    发明授权
    Semiconductor devices with strained source/drain structures 有权
    具有应变源/漏结构的半导体器件

    公开(公告)号:US08796788B2

    公开(公告)日:2014-08-05

    申请号:US13009322

    申请日:2011-01-19

    IPC分类号: H01L29/772

    摘要: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved source/drain features in the semiconductor device. Semiconductor devices with the improved source/drain features may prevent or reduce defects and achieve high strain effect resulting from epi layers. In an embodiment, the source/drain features comprises a second portion surrounding a first portion, and a third portion between the second portion and the semiconductor substrate, wherein the second portion has a composition different from the first and third portions.

    摘要翻译: 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供了用于在半导体器件中形成改进的源极/漏极特征的处理。 具有改善的源极/漏极特征的半导体器件可以防止或减少缺陷并实现由epi层产生的高应变效应。 在一个实施例中,源极/漏极特征包括围绕第一部分的第二部分和在第二部分和半导体衬底之间的第三部分,其中第二部分具有不同于第一和第三部分的组成。