公开(公告)号：US20070044544A1

公开(公告)日：2007-03-01

申请号：US11420325

申请日：2006-05-25

申请人： Dmytro Chumakov ,  Holm Geisler ,  Ehrenfried Zschech

发明人： Dmytro Chumakov ,  Holm Geisler ,  Ehrenfried Zschech

IPC分类号： G01B5/28

CPC分类号： G01Q60/32

摘要： By digitizing the UFM signal without using a lock-in amplifier, substantially all of the information initially contained in the UFM output signal may be maintained and may then be used for further data processing. Consequently, any type of model or evaluation algorithm may be used without being restricted to a very narrow bandwidth, as is the case in lock-in based techniques. The digitizing is performed on a real-time basis, wherein a complete UFM curve is digitized and stored for each scan position. In this way, quantitative meaningful values for specific surface-related characteristics with a nanometer resolution may be obtained.

摘要翻译： 通过在不使用锁定放大器的情况下数字化UFM信号，可以维持初始包含在UFM输出信号中的所有信息，然后可以用于进一步的数据处理。 因此，可以使用任何类型的模型或评估算法而不限于非常窄的带宽，如基于锁定的技术的情况。 实时执行数字化，其中为每个扫描位置数字化和存储完整的UFM曲线。 以这种方式，可以获得具有纳米分辨率的特定表面相关特征的定量有意义的值。

公开(公告)号：US07441446B2

公开(公告)日：2008-10-28

申请号：US11420325

申请日：2008-05-25

申请人： Dmytro Chumakov ,  Holm Geisler ,  Ehrenfried Zschech

发明人： Dmytro Chumakov ,  Holm Geisler ,  Ehrenfried Zschech

IPC分类号： G01H3/12

CPC分类号： G01Q60/32

摘要： By digitizing the UFM signal without using a lock-in amplifier, substantially all of the information initially contained in the UFM output signal may be maintained and may then be used for further data processing. Consequently, any type of model or evaluation algorithm may be used without being restricted to a very narrow bandwidth, as is the case in lock-in based techniques. The digitizing is performed on a real-time basis, wherein a complete UFM curve is digitized and stored for each scan position. In this way, quantitative meaningful values for specific surface-related characteristics with a nanometer resolution may be obtained.

摘要翻译： 通过在不使用锁定放大器的情况下数字化UFM信号，可以维持初始包含在UFM输出信号中的所有信息，然后可以用于进一步的数据处理。 因此，可以使用任何类型的模型或评估算法而不限于非常窄的带宽，如基于锁定的技术的情况。 实时执行数字化，其中为每个扫描位置数字化和存储完整的UFM曲线。 以这种方式，可以获得具有纳米分辨率的特定表面相关特征的定量有意义的值。

公开(公告)号：US08946019B2

公开(公告)日：2015-02-03

申请号：US12965212

申请日：2010-12-10

申请人： Dmytro Chumakov ,  Tino Hertzsch

发明人： Dmytro Chumakov ,  Tino Hertzsch

IPC分类号： H01L21/8242 ,  H01L27/06 ,  H01L23/522

CPC分类号： H01L27/0629 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device, capacitors may be formed so as to be in direct contact with a transistor by using a shared transistor region, such as a drain region or a source region of closely spaced transistors, as one capacitor electrode, while the other capacitor electrode is provided in the form of a buried electrode in the dielectric material of the contact level. To this end, dielectric material may be deposited so as to reliably form a void, wherein, at any appropriate manufacturing stage, a capacitor dielectric material may be provided so as to separate the capacitor electrodes.

摘要翻译： 在半导体器件中，可以通过使用诸如漏极区域或紧密间隔的晶体管的源极区域的共享晶体管区域作为一个电容器电极来形成电容器以与晶体管直接接触，而另一个电容器电极 以接触电平的电介质材料中的埋入电极的形式提供。 为此，可以沉积电介质材料以便可靠地形成空隙，其中，在任何适当的制造阶段，可以提供电容器电介质材料以分离电容器电极。

公开(公告)号：US08748199B2

公开(公告)日：2014-06-10

申请号：US13092815

申请日：2011-04-22

申请人： Dmytro Chumakov

发明人： Dmytro Chumakov

IPC分类号： H01L21/66

CPC分类号： G01B11/24 ,  G01B2210/56 ,  H01L22/12 ,  H01L22/26

摘要： Methods and systems are provided for fabricating a semiconductor device. An exemplary method involves forming a feature of a semiconductor device in a first region of a layer of material on a semiconductor substrate and forming a test structure in a second region of the layer of material. The test structure is formed concurrently to forming the feature, and a dimension of the feature is determined using the test structure.

摘要翻译： 提供了用于制造半导体器件的方法和系统。 一种示例性方法包括在半导体衬底上的材料层的第一区域中形成半导体器件的特征，并在该材料层的第二区域中形成测试结构。 测试结构与形成特征同时形成，并且使用测试结构确定特征的尺寸。

公开(公告)号：US08925396B2

公开(公告)日：2015-01-06

申请号：US12725688

申请日：2010-03-17

申请人： Petra Hetzer ,  Matthias Schaller ,  Dmytro Chumakov

发明人： Petra Hetzer ,  Matthias Schaller ,  Dmytro Chumakov

IPC分类号： G01N1/04 ,  G01N1/02 ,  G01N15/00 ,  H01L21/66

CPC分类号： G01N1/02 ,  G01N2001/028 ,  G01N2015/0038 ,  H01L22/12

摘要： During the fabrication of microstructure devices, such as integrated circuits, particles may be analyzed by displacing or removing the particles from the device surface and subsequently performing an analysis process. Consequently, a well-defined measurement environment may be established after removal of the particles, which may be accomplished on the basis of nanoprobes and the like. Hence, even critical surface areas may be monitored with respect to contamination and the like on the basis of well-established analysis techniques.

摘要翻译： 在诸如集成电路的微结构器件的制造期间，可以通过从器件表面移位或移除颗粒并随后执行分析过程来分析颗粒。 因此，可以在去除颗粒之后建立明确的测量环境，这可以基于纳米探针等来实现。 因此，即使关键的表面积也可以基于已知的分析技术来监测污染等。

公开(公告)号：US08785271B2

公开(公告)日：2014-07-22

申请号：US13017682

申请日：2011-01-31

申请人： Dmytro Chumakov ,  Wolfgang Buchholtz ,  Petra Hetzer

发明人： Dmytro Chumakov ,  Wolfgang Buchholtz ,  Petra Hetzer

IPC分类号： H01L21/8242

CPC分类号： H01L27/1082 ,  B82Y10/00 ,  H01L27/10852 ,  H01L28/90

摘要： A capacitor is formed in nano channels in a conductive body. Embodiments include forming a source contact through a first inter layer dielectric (ILD), forming a conductive body on the first ILD, forming a second ILD on the conductive body, forming drain and gate contacts through the second ILD, conductive body, and first ILD, forming nano channels in the conductive body, forming an insulating layer in the channels, and metalizing the channels. An embodiment includes forming the nano channels by forming a mask on the second ILD, the mask having features with a pitch of 50 nanometers (nm) to 100 nm, etching the second ILD through the mask, etching the conductive body through the mask to a depth of 80% to 90% of the thickness of the conductive body, and removing the mask.

摘要翻译： 在导电体中的纳米通道中形成电容器。 实施例包括通过第一层间电介质（ILD）形成源极接触，在第一ILD上形成导电体，在导电体上形成第二ILD，通过第二ILD，导电体和第一ILD形成漏极和栅极接触 在导电体中形成纳米通道，在通道中形成绝缘层，并使通道金属化。 一个实施方案包括通过在第二ILD上形成掩模形成纳米通道，该掩模具有50纳米（nm）至100nm的间距的特征，通过掩模蚀刻第二ILD，通过掩模将导电体蚀刻到 深度为导电体的厚度的80％至90％，并且去除掩模。

公开(公告)号：US08569171B2

公开(公告)日：2013-10-29

申请号：US13175709

申请日：2011-07-01

申请人： Dmytro Chumakov

发明人： Dmytro Chumakov

IPC分类号： H01L21/337

CPC分类号： H01L21/28518 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/665 ,  H01L29/78

摘要： A semiconductor device with reduced defect density is fabricated by forming localized metal silicides instead of full area silicidation. Embodiments include forming a transistor having a gate electrode and source/drain regions on a substrate, forming a masking layer with openings exposing portions of both the gate electrode and source/drain regions over the substrate, depositing metal in the openings on the exposed portions, forming silicides in the openings, and removing unreacted metal and the masking layer.

摘要翻译： 通过形成局部金属硅化物而不是全面的硅化物来制造具有降低的缺陷密度的半导体器件。 实施例包括在衬底上形成具有栅极电极和源极/漏极区域的晶体管，形成掩模层，该掩模层具有使基板上的栅极电极和源极/漏极区域的部分露出的开口，在暴露部分上的开口中沉积金属， 在开口中形成硅化物，并除去未反应的金属和掩蔽层。

公开(公告)号：US08497583B2

公开(公告)日：2013-07-30

申请号：US12964448

申请日：2010-12-09

申请人： Dmytro Chumakov ,  Michael Grillberger ,  Heike Berthold ,  Katrin Reiche

发明人： Dmytro Chumakov ,  Michael Grillberger ,  Heike Berthold ,  Katrin Reiche

IPC分类号： H01L29/40

CPC分类号： H01L23/562 ,  H01L2224/16225 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00

摘要： A stress compensation region that may be appropriately positioned on a package substrate may compensate for or at least significantly reduce the thermally induced mechanical stress in a sensitive metallization system of a semiconductor die, in particular during the critical reflow process. For example, a stressor ring may be formed so as to laterally surround the chip receiving portion of the package substrate, wherein the stressor ring may efficiently compensate for the thermally induced deformation in the chip receiving portion.

摘要翻译： 可以适当地定位在封装衬底上的应力补偿区域可以补偿或至少显着地降低半导体管芯的敏感金属化系统中的热致机械应力，特别是在临界回流工艺期间。 例如，应力环可以形成为横向围绕封装衬底的芯片接收部分，其中应力环可以有效地补偿芯片接收部分中的热诱导变形。

公开(公告)号：US20110291298A1

公开(公告)日：2011-12-01

申请号：US12964359

申请日：2010-12-09

申请人： Dmytro Chumakov

发明人： Dmytro Chumakov

IPC分类号： H01L23/58 ,  H01L21/50

CPC分类号： H01L24/81 ,  H01L23/13 ,  H01L23/4985 ,  H01L24/17 ,  H01L2224/131 ,  H01L2224/1703 ,  H01L2224/81815 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2224/13099 ,  H01L2924/00

摘要： Thermally induced stress in a semiconductor die, i.e., in a complex metallization system thereof, may be reduced by “dividing” a package substrate into two or more substrate sections, which may have formed therebetween an appropriate stress buffer region, for instance a region of superior resiliency. In this case, the total deformation of the package substrate may be reduced, thereby also reducing the thermally induced stress forces in the complex metallization system of the semiconductor die. Hence, for a given size and complexity of a metallization system, an increased production yield and superior reliability may be achieved.

摘要翻译： 可以通过将封装衬底“划分”为两个或更多个衬底部分来减少半导体管芯中的热致应力，即其复杂的金属化系统，这两个或多个衬底部分可能在其间形成适当的应力缓冲区域，例如， 卓越的弹性。 在这种情况下，可以减小封装基板的总变形，从而也降低半导体管芯的复合金属化系统中的热诱导应力。 因此，对于给定尺寸和金属化系统的复杂性，可以实现提高的产量和优异的可靠性。

公开(公告)号：US09070639B2

公开(公告)日：2015-06-30

申请号：US13069488

申请日：2011-03-23

申请人： Dmytro Chumakov ,  Volker Grimm

发明人： Dmytro Chumakov ,  Volker Grimm

IPC分类号： H01L21/311 ,  H01L21/033 ,  H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816

摘要： In sophisticated semiconductor devices, manufacturing techniques and etch masks may be formed on the basis of a mask layer stack which comprises an additional mask layer, which may receive an opening on the basis of lithography techniques. Thereafter, the width of the mask opening may be reduced by applying a selective deposition or growth process, which thus results in a highly uniform and well-controllable adjustment of the target width of the etch mask prior to performing the actual patterning process, for instance for forming sophisticated contact openings, via openings and the like.

摘要翻译： 在复杂的半导体器件中，可以基于掩模层堆叠形成制造技术和蚀刻掩模，掩模层堆叠包括附加的掩模层，其可以基于光刻技术接收开口。 此后，可以通过施加选择性沉积或生长工艺来减小掩模开口的宽度，从而在执行实际图案化工艺之前导致对蚀刻掩模的目标宽度的高度均匀和良好可控的调整，例如 用于形成复杂的接触开口，通孔等。