公开(公告)号：US5504434A

公开(公告)日：1996-04-02

申请号：US453590

申请日：1995-05-30

申请人： Dominic J. Schepis ,  Krishna Seshan

发明人： Dominic J. Schepis ,  Krishna Seshan

IPC分类号： H01L21/48 ,  H01L21/66 ,  G01R31/26

CPC分类号： H01L22/14 ,  H01L21/485 ,  H01L22/22

摘要： A measurement technique and instrument using rectangular pulse trains of differing repetition rates and synchronously operated lock-in amplifiers to reject electrical noise and capture changes in resistance and capacitance of an electrical element even during a short electrical pulse applied thereto or in the presence of high levels of electrical noise. Particular applications are for electrical programming of fuses and repair of conductors by material deposition.

摘要翻译： 使用不同重复率的矩形脉冲串和同步操作的锁定放大器的测量技术和仪器，以抵抗电气噪声，并捕获电子元件的电阻和电容的变化，即使在施加到其上的短电脉冲中或存在高电平 的电噪声。 特殊应用是用于熔丝的电气编程和通过材料沉积修复导体。

公开(公告)号：US5614440A

公开(公告)日：1997-03-25

申请号：US419778

申请日：1995-04-11

申请人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

发明人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

IPC分类号： H01H85/00 ,  H01H85/02 ,  H01H85/046 ,  H01H85/12 ,  H01L23/525 ,  H01L23/58 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  Y10S148/055

摘要： A method of fabricating a noise immune fuse having sub-micron dimensions which can be programmed by an electrically and thermally synchronized event. The fuse includes a pair of fuse links in close proximity of each other, a layer of thermally conductive and electrically insulating material thermally coupling the two links forming the pair, and means for programming the first link by prompting the second link to gate the energy transfer between the links via the coupling layer. By combining thermal and electrical pulses to perform the programming function, the reliability of the fuse structure is greatly enhanced when compared to that of a single element fuse.

摘要翻译： 一种制造具有亚微米尺寸的噪声免疫熔丝的方法，其可以通过电和热同步事件来编程。 熔丝包括彼此紧密相邻的一对熔丝链，热耦合形成该对的两个连接的导热和电绝缘材料层，以及用于通过提示第二连接件对能量传递进行栅极编程的装置 通过耦合层在链路之间。 通过组合热和电脉冲来执行编程功能，与单个元件熔断器相比，熔丝结构的可靠性大大提高。

公开(公告)号：US5622892A

公开(公告)日：1997-04-22

申请号：US407431

申请日：1995-03-17

申请人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

发明人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

IPC分类号： H01L21/82 ,  H01L23/367 ,  H01L23/525 ,  H01L21/306 ,  H01L21/326

CPC分类号： H01L23/5256 ,  H01L23/3672 ,  H01L2924/0002 ,  Y10S438/922

摘要： A method of fabricating an electrically programmable fuse buried under quartz and layers of polyimide with a specific structure to enhance its "thermal" capabilities. The fuse is designed to "blow" and cool off quickly so as not to cause damage to areas above and surrounding the fuse. A passivation layer is added above the fuse to act as a heat sink and absorb and redistribute the heat generated from one localized area to a broader and cooler area. The materials used for the fuse and the heat sink are selected to be compatible with both oxide and polyimide personalization schemes. Modeling of the fuse enables optimizing the characteristics of the fuse, particularly to transmit to the surface of the passivation layer the thermal wave created during programming of the fuse.

摘要翻译： 埋设在石英下的电可编程熔丝的制造方法和具有特定结构的聚酰亚胺层以提高其“热”能力。 保险丝设计为“吹”并快速冷却，以免对保险丝上方和周围的区域造成损坏。 保险丝上方加上钝化层，作为散热片，吸收并重新分配从一个局部区域产生的热量到较宽和较冷的区域。 用于保险丝和散热器的材料被选择为与氧化物和聚酰亚胺个性化方案兼容。 保险丝的建模可以优化保险丝的特性，特别是在保险丝编程期间向钝化层的表面传输热波。

公开(公告)号：US5585663A

公开(公告)日：1996-12-17

申请号：US511565

申请日：1995-08-04

申请人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

发明人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

IPC分类号： H01L21/82 ,  H01L23/367 ,  H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L23/3672 ,  H01L2924/0002 ,  Y10S438/922

摘要： An electrically programmable fuse buried under quartz and layers of polyimide with a specific structure to enhance its "thermal" capabilities. The fuse is designed to "blow" and cool off quickly so as not to cause damage to areas above and surrounding the fuse. A passivation layer is added above the fuse to act as a heat sink and absorb and redistribute the heat generated from one localized area to a broader and cooler area. The materials used for the fuse and the heat sink are selected to be compatible with both oxide and polyimide personalization schemes. Modeling of the fuse enables optimizing the characteristics of the fuse, particularly to transmit to the surface of the passivation layer the thermal wave created during programming of the fuse.

摘要翻译： 埋在石英下的电可编程熔丝和具有特定结构的聚酰亚胺层，以增强其“热”能力。 保险丝设计为“吹”并快速冷却，以免对保险丝上方和周围的区域造成损坏。 保险丝上方加上钝化层，作为散热片，吸收并重新分配从一个局部区域产生的热量到较宽和较冷的区域。 用于保险丝和散热器的材料被选择为与氧化物和聚酰亚胺个性化方案兼容。 保险丝的建模可以优化保险丝的特性，特别是在保险丝编程期间向钝化层的表面传输热波。

公开(公告)号：US5444287A

公开(公告)日：1995-08-22

申请号：US292901

申请日：1994-08-10

申请人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

发明人： Raschid J. Bezama ,  Dominic J. Schepis ,  Krishna Seshan

IPC分类号： H01H85/00 ,  H01H85/02 ,  H01H85/046 ,  H01H85/12 ,  H01L23/525 ,  H01L23/58 ,  H01L29/167 ,  H01L23/48 ,  H01L29/207

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  Y10S148/055

摘要： A noise immune fuse having sub-micron dimensions which can be programmed by an electrically and thermally synchronized event. The fuse includes a pair of fuse links in close proximity of each other, a layer of thermally conductive and electrically insulating material thermally coupling the two links forming the pair, and means for programming the first link by prompting the second link to gate the energy transfer between the links via the coupling layer. By combining thermal and electrical pulses to perform the programming function, the reliability of the fuse structure is greatly enhanced when compared to that of a single element fuse.

摘要翻译： 具有亚微米尺寸的噪声免疫保险丝，可通过电和热同步事件进行编程。 熔丝包括彼此紧密相邻的一对熔丝链，热耦合形成该对的两个连接的导热和电绝缘材料层，以及用于通过提示第二连接件对能量传递进行栅极编程的装置 通过耦合层在链路之间。 通过组合热和电脉冲来执行编程功能，与单个元件熔断器相比，熔丝结构的可靠性大大提高。

公开(公告)号：US5298784A

公开(公告)日：1994-03-29

申请号：US858835

申请日：1992-03-27

申请人： Jeffrey P. Gambino ,  Dominic J. Schepis ,  Krishna Seshan

发明人： Jeffrey P. Gambino ,  Dominic J. Schepis ,  Krishna Seshan

IPC分类号： H01L21/82 ,  H01L23/525 ,  H01L23/48

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L2924/0002

摘要： An improved antifuse uses metal penetration of either a P-N diode junction or a Schottky diode. The P-N junction, or Schottky diode, is contacted by a diffusion barrier such as TiN, W, Ti-W alloy, or layers of Ti and Cr, with a metal such as Al. Al-CU alloy, Cu, Au, or Ag on top of the diffusion barrier. When this junction is stressed with voltage pulse producing a high current density, severe joule heating occurs resulting in metal penetration of the diffusion barrier and the junction. The voltage drop across the junction decreases by about a factor of ten after the current stress and is stable thereafter. Alternatively, a shallow P-N junction in a silicon substrate is contacted by a layer of metal that forms a silicide, such as Ti, Cr, W, Mo, or Ta. Stressing the junction with a voltage pulse to produce a high current density results in the metal penetrating the junction and reacting with the substrate to form a silicide.

摘要翻译： 改进的反熔丝使用P-N二极管结或肖特基二极管的金属穿透。 P-N结或肖特基二极管通过诸如TiN，W，Ti-W合金或Ti和Cr的层的扩散阻挡层与诸如Al的金属接触。 Al-Cu合金，Cu，Au或Ag在扩散阻挡层的顶部。 当该结被电压脉冲施加而产生高电流密度时，发生严重的焦耳加热，导致扩散阻挡层和结的金属穿透。 跨接点的电压降在电流应力之后减少约十倍，此后稳定。 或者，硅衬底中的浅P-N结与由Ti，Cr，W，Mo或Ta形成硅化物的金属层接触。 用电压脉冲强加结以产生高电流密度导致金属穿透接合部并与衬底反应形成硅化物。

公开(公告)号：US08685845B2

公开(公告)日：2014-04-01

申请号：US12860236

申请日：2010-08-20

申请人： Abhishek Dube ,  Ashima B. Chakravarti ,  Jinghong H. Li ,  Rainer Loesing ,  Dominic J. Schepis

发明人： Abhishek Dube ,  Ashima B. Chakravarti ,  Jinghong H. Li ,  Rainer Loesing ,  Dominic J. Schepis

IPC分类号： H01L21/20

CPC分类号： H01L21/0262 ,  H01L21/0237 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02587 ,  H01L21/02636 ,  H01L29/045 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7848

摘要： A method for depositing epitaxial films of silicon carbon (Si:C). In one embodiment, the method includes depositing an n-type doped silicon carbon (Si:C) semiconductor material on a semiconductor deposition surface using a deposition gas precursor composed of a silane containing gas precursor, a carbon containing gas precursor, and an n-type gas dopant source. The deposition gas precursor is introduced to the semiconductor deposition surface with a hydrogen (H2) carrier gas. The method for depositing epitaxial films may include an etch reaction provided by hydrogen chloride (HCl) gas etchant and a hydrogen (H2) carrier gas.

摘要翻译： 一种用于沉积硅碳外延膜（Si：C）的方法。 在一个实施例中，该方法包括：使用由含硅烷的气体前体，含碳气体前体和正极材料构成的沉积气体前体，在半导体沉积表面上沉积n型掺杂硅碳（Si：C） 型气体掺杂剂源。 沉积气体前体用氢（H 2）载气引入半导体沉积表面。 沉积外延膜的方法可以包括由氯化氢（HCl）气体蚀刻剂和氢（H 2）载气提供的蚀刻反应。

公开(公告)号：US08652925B2

公开(公告)日：2014-02-18

申请号：US12838515

申请日：2010-07-19

申请人： Oh-Jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Dominic J. Schepis

发明人： Oh-Jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Dominic J. Schepis

IPC分类号： H01L21/20

CPC分类号： H01L21/2007 ,  G06F17/5068 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/76251 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/40 ,  H01L28/90 ,  H01L29/66181

摘要： A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

摘要翻译： 提供了用于制造隔离电容器的结构和方法。 该方法包括同时形成多个深沟槽和围绕多个深沟槽的一组或多个阵列的一个或多个隔离沟槽，其通过SOI和掺杂多晶硅层形成到下面的绝缘体层。 该方法还包括用绝缘体材料衬套多个深沟槽和一个或多个隔离沟槽。 该方法还包括在绝缘体材料上用导电材料填充多个深沟槽和一个或多个隔离沟槽。 深沟槽形成深沟槽电容器，并且一个或多个隔离沟槽形成一个或多个隔离板，其将深沟槽电容器的至少一组或阵列与另一组或深沟槽电容器阵列隔离开来。

公开(公告)号：US20120205749A1

公开(公告)日：2012-08-16

申请号：US13025474

申请日：2011-02-11

申请人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

发明人： Ashima B. Chakravarti ,  Abhishek Dube ,  Dominic J. Schepis

IPC分类号： H01L27/092 ,  H01L21/762 ,  H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/76224 ,  H01L21/823807

摘要： Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.

摘要翻译： 在不使用掩模的情况下实现硅锗在半导体器件中的外延沉积。 使用在沉积硅锗之前与存在的掺杂剂的相互作用引起的成核延迟来确定暴露的衬底表面可以经历外延沉积以在所需部分上形成SiGe层的周期，而在其它部分上基本上没有沉积。 可以改变掺杂剂浓度以在优选的沉积时间内实现期望的厚度。 导致沉积的SiGe基本上没有生长边缘效应。

公开(公告)号：US08232186B2

公开(公告)日：2012-07-31

申请号：US12128955

申请日：2008-05-29

申请人： Eric C. T. Harley ,  Judson R. Holt ,  Dominic J. Schepis ,  Michael D. Steigerwalt ,  Linda Black ,  Rick Carter

发明人： Eric C. T. Harley ,  Judson R. Holt ,  Dominic J. Schepis ,  Michael D. Steigerwalt ,  Linda Black ,  Rick Carter

IPC分类号： H01L21/20

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66636 ,  H01L29/7848

摘要： Methods of integrating reverse embedded silicon germanium (SiGe) on an NFET and SiGe channel on a PFET, and a related structure are disclosed. One method may include providing a substrate including an NFET area and a PFET area; performing a single epitaxial growth of a silicon germanium (SiGe) layer over the substrate; forming an NFET in the NFET area, the NFET including a SiGe plug in a channel thereof formed from the SiGe layer; and forming a PFET in the PFET area, the PFET including a SiGe channel formed from the SiGe layer. As an option, the SiGe layer over the PFET area may be thinned.

摘要翻译： 公开了在NFET和PFET上的SiGe沟道上集成反向嵌入硅锗（SiGe）的方法和相关结构。 一种方法可以包括提供包括NFET区域和PFET区域的衬底; 在衬底上执行硅锗（SiGe）层的单个外延生长; 在NFET区域中形成NFET，NFET在由SiGe层形成的沟道中包括SiGe插塞; 以及在PFET区中形成PFET，PFET包括由SiGe层形成的SiGe沟道。 作为选择，PFET区域上的SiGe层可能变薄。