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    Conductor track configuration for very large-scale integrated circuits
    1.
    发明授权
    Conductor track configuration for very large-scale integrated circuits 失效
    针对非常大型集成电路的导体轨道配置

    公开(公告)号：US5289037A

    公开(公告)日：1994-02-22

    申请号：US883113

    申请日：1992-05-14

    申请人： Dominique Savignac ,  Manfred Menke ,  Armin Kohlhase ,  Hanno Melzner

    发明人： Dominique Savignac ,  Manfred Menke ,  Armin Kohlhase ,  Hanno Melzner

    IPC分类号： H01L21/82 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L27/108 ,  H01L23/48

    CPC分类号： H01L23/5226 ,  H01L23/528 ,  H01L2924/0002

    摘要： A conductor track configuration for very large-scale integrated circuits includes at least two lower conductor tracks extending substantially in a first direction and at least two upper conductor tracks extending substantially in the first direction above the lower conductor tracks. Each of the lower conductor tracks is subdivided into segments, defining gaps between the segments. Each respective one of the segments has one contact leading to the upper conductor track disposed above the one segment. The lower conductor tracks adjacent the segments, as seen in a second direction, have one of the gaps at least in the vicinity of one of the contacts.

    摘要翻译： 用于非常大规模的集成电路的导体轨道配置包括至少两个基本上沿第一方向延伸的下部导体轨道和至少两个上部导体轨道，其基本上沿着下部导体轨道的第一方向延伸。 每个下导体轨道被细分成段，限定段之间的间隙。 每个分段中的每一个具有通向设置在一个段上方的上部导体轨迹的一个触点。 至少在其中一个接触点附近，沿着第二方向看到的邻近片段的下导体迹线具有一个间隙。

    Method for producing a memory device
    2.
    发明授权
    Method for producing a memory device 失效
    存储器件的制造方法

    公开(公告)号：US6100109A

    公开(公告)日：2000-08-08

    申请号：US81910

    申请日：1998-05-20

    申请人： Hanno Melzner ,  Armin Kohlhase

    发明人： Hanno Melzner ,  Armin Kohlhase

    IPC分类号： B81B3/00 ,  G11C23/00 ,  H01H1/00 ,  H01L21/00

    CPC分类号： H01H1/0036 ,  G11C23/00 ,  H01H2001/0042

    摘要： A memory device includes a multiplicity of memory cells disposed on a substrate for at least intermittent stable storage of at least two different information states. A writing device is associated with the memory cells for selectively putting one of the multiplicity of memory cells into a predetermined information state by external action. A reading device is associated with the memory cells for external detection of a current or chronologically preceding information state of a selected memory cell. The memory cells have a miniaturized mechanical element. The production of such a memory device is performed with the following steps: full-surface application of a first insulator layer onto a main surface of a substrate; full-surface application of a diaphragm layer being formed of an electrically conductive material onto the first insulator layer; structuring of the diaphragm layer in such a way that first conductor tracks are formed, which have enlargements at points of the memory cells; isotropic etching of the first insulator layer, using the structured diaphragm layer as an etching mask, until such time as a sharp point remains behind in the middle, immediately beneath the enlargement; and removal of all of the material of the fist insulator layer on the underside of the enlargement, thus forming a diaphragm.

    摘要翻译： 存储器件包括设置在衬底上的多个存储器单元，用于至少间歇地稳定地存储至少两个不同的信息状态。 写入装置与存储器单元相关联，用于通过外部动作选择性地将多个存储器单元中的一个置于预定信息状态。 读取装置与存储器单元相关联，用于外部检测所选择的存储器单元的当前或按时间顺序排列的先前信息状态。 存储单元具有小型化的机械元件。 这样的存储器件的制造通过以下步骤进行：将第一绝缘体层全面地施加到衬底的主表面上; 将由导电材料形成的隔膜层全表面施加到第一绝缘体层上; 以形成第一导体轨道的方式构造隔膜层，其在存储器单元的点处具有放大; 第一绝缘体层的各向同性蚀刻，使用结构化的膜层作为蚀刻掩模，直到在尖端的时间保留在中间的正下方的放大图; 并且在放大图的下侧去除第一绝缘体层的所有材料，从而形成隔膜。

    Semiconductor memory device having a transistor, a bit line, a word line and a stacked capacitor
    3.
    发明授权
    Semiconductor memory device having a transistor, a bit line, a word line and a stacked capacitor 失效
    具有晶体管，位线，字线和层叠电容器的半导体存储器件

    公开(公告)号：US5714779A

    公开(公告)日：1998-02-03

    申请号：US730644

    申请日：1996-10-11

    申请人： Stephan Auer ,  Armin Kohlhase ,  Hanno Melzner

    发明人： Stephan Auer ,  Armin Kohlhase ,  Hanno Melzner

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L27/04 ,  H01L29/92

    CPC分类号： H01L27/10852

    摘要： A semiconductor memory configuration and a manufacturing process for the semiconductor memory configuration use a polishing process in the manufacture of a semiconductor memory configuration with stacked-capacitor-above-bit-line memory cells. At least TC pillars are created with the aid of a CMP step and a completely planarized surface existing prior to the manufacture of the bit line. Further CMP steps are advantageously used, inter alia, in the manufacture of a TB pillar of a bit line which is countersunk in a trench and of a lower capacitor plate, as well as to completely planarize a cell array and a periphery prior to interconnection of the circuit.

    摘要翻译： 用于半导体存储器配置的半导体存储器配置和制造工艺在制造具有叠层电容器 - 位线存储器单元的半导体存储器配置中使用抛光工艺。 借助于CMP步骤和在制造位线之前存在的完全平坦化的表面，至少创建TC柱。 有利地使用其它CMP步骤，特别是在制造在沟槽和下电容器板中沉没的位线的TB柱以及在互连之前完全平坦化单元阵列和周边 电路。

    Integrated semiconductor circuit or micromechanical component and process therefore
    4.
    发明授权
    Integrated semiconductor circuit or micromechanical component and process therefore 失效
    因此，集成半导体电路或微机械元件和工艺

    公开(公告)号：US5623164A

    公开(公告)日：1997-04-22

    申请号：US360803

    申请日：1995-05-10

    申请人： Stephan Auer ,  Armin Kohlhase ,  Hanno Melzner

    发明人： Stephan Auer ,  Armin Kohlhase ,  Hanno Melzner

    IPC分类号： H01L21/8242 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/822 ,  H01L27/04 ,  H01L27/108 ,  H01L29/92

    CPC分类号： H01L21/31053

    摘要： For the global planarization of a semiconductor circuit or a micromechanical component with a step between a higher-lying region and a lower-lying region, the regions being large in area, it is envisaged to deposit a first layer (50), remove it again in the higher-lying region apart from a rib (50), deposit a second layer (51) and then, in a CMP step, planarize the entire arrangement.

    摘要翻译： PCT No.PCT / DE93 / 00553 Sec。 371日期：1995年5月10日 102（e）日期1995年5月10日PCT提交1993年6月24日PCT公布。 公开号WO94 / 00876 日期1994年1月6日对于半导体电路或微机械部件的全局平面化，其具有在较高位置区域和较低位置区域之间的台阶，该区域面积大，可以设想沉积第一层（50 ），在远离肋（50）的较高位置区域中再次移除，沉积第二层（51），然后在CMP步骤中平整整个布置。

    Memory device and production method
    5.
    发明授权
    Memory device and production method 失效
    内存设备和生产方式

    公开(公告)号：US5774414A

    公开(公告)日：1998-06-30

    申请号：US694531

    申请日：1996-08-09

    申请人： Hanno Melzner ,  Armin Kohlhase

    发明人： Hanno Melzner ,  Armin Kohlhase

    IPC分类号： G11C11/22 ,  G11C11/24 ,  G11C23/00 ,  G11C7/00

    CPC分类号： G11C11/22 ,  G11C11/24 ,  G11C23/00 ,  H01H2001/0042

    摘要： A memory device includes a multiplicity of memory cells disposed on a substrate for at least intermittent stable storage of at least two different information states. A writing device is associated with the memory cells for selectively putting one of the multiplicity of memory cells into a predetermined information state by external action. A reading device is associated with the memory cells for external detection of a current or chronologically preceding information state of a selected memory cell. The memory cells have a miniaturized mechanical element. The production of such a memory device is performed with the following steps: full-surface application of a first insulator layer onto a main surface of a substrate; full-surface application of a diaphragm layer being formed of an electrically conductive material onto the first insulator layer; structuring of the diaphragm layer in such a way that first conductor tracks are formed, which have enlargements at points of the memory cells; isotropic etching of the first insulator layer, using the structured diaphragm layer as an etching mask, until such time as a sharp point remains behind in the middle, immediately beneath the enlargement; and removal of all of the material of the fist insulator layer on the underside of the enlargement, thus forming a diaphragm.

    摘要翻译： 存储器件包括设置在衬底上的多个存储器单元，用于至少间歇地稳定地存储至少两个不同的信息状态。 写入装置与存储器单元相关联，用于通过外部动作选择性地将多个存储器单元中的一个置于预定信息状态。 读取装置与存储器单元相关联，用于外部检测所选择的存储器单元的当前或按时间顺序排列的先前信息状态。 存储单元具有小型化的机械元件。 这样的存储器件的制造通过以下步骤进行：将第一绝缘体层全面地施加到衬底的主表面上; 将由导电材料形成的隔膜层全表面施加到第一绝缘体层上; 以形成第一导体轨道的方式构造隔膜层，其在存储器单元的点处具有放大; 第一绝缘体层的各向同性蚀刻，使用结构化的膜层作为蚀刻掩模，直到在尖端的时间保留在中间的正下方的放大图; 并且在放大图的下侧去除第一绝缘体层的所有材料，从而形成隔膜。

    Semiconductor memory having charge trapping memory cells and fabrication method
    7.
    发明申请
    Semiconductor memory having charge trapping memory cells and fabrication method 有权
    具有电荷捕获存储单元的半导体存储器和制造方法

    公开(公告)号：US20050286296A1

    公开(公告)日：2005-12-29

    申请号：US11145541

    申请日：2005-06-03

    申请人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    发明人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

    IPC分类号： H01L21/8246 ,  H01L27/115 ,  G11C11/34

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

    摘要翻译： 在具有NROM单元的半导体存储器的情况下，存储晶体管的沟道区域在每种情况下相对于相关字线横向延伸，位线布置在字线的顶侧并且以电绝缘的方式 并且存在导电交叉连接，这些交叉连接被布置在字线之间的间隔中并且以与后者的电绝缘的方式布置，并且在下一个序列中在每种情况下连接到位线。

    Memory cell configuration and corresponding production process
    8.
    发明授权
    Memory cell configuration and corresponding production process 失效
    内存单元配置及相应的生产流程

    公开(公告)号：US06472696B1

    公开(公告)日：2002-10-29

    申请号：US09645763

    申请日：2000-08-25

    申请人： Ulrich Zimmermann ,  Thomas Böhm ,  Manfred Hain ,  Armin Kohlhase ,  Yoichi Otani ,  Andreas Rusch ,  Alexander Trüby

    发明人： Ulrich Zimmermann ,  Thomas Böhm ,  Manfred Hain ,  Armin Kohlhase ,  Yoichi Otani ,  Andreas Rusch ,  Alexander Trüby

    IPC分类号： H01L2710

    CPC分类号： H01L27/11273 ,  H01L27/112

    摘要： The memory cell configuration has a large number of memory cells provided in a semiconductor substrate and having bit-line trenches which extend in parallel in the longitudinal direction in the main face of the semiconductor substrate, at the bottoms of which in each case a first conductive region is provided, at the peaks of which in each case a second conductive region of the same conduction type as the first conductive region is provided, and in the walls of which in each case an intermediately located channel region is 0 provided; and having word lines which extend in the transverse direction along the main face of the semiconductor substrate, through specific bit-line trenches, to activate transistors provided there. An additional dopant is introduced into the trench walls of the bit-line trenches which are located between the word lines, in order to increase the corresponding transistor turn-on voltage there to suppress leakage currents.

    摘要翻译： 存储单元配置具有设置在半导体衬底中的大量存储单元，并且具有在半导体衬底的主面中在纵向方向上平行延伸的位线沟槽，其底部在每种情况下都具有第一导电 区域被提供，其峰值在每种情况下具有与第一导电区域相同的导电类型的第二导电区域，并且在其每一种情况下壁的中间位置的沟道区域为0; 并且具有通过特定位线沟槽沿着半导体衬底的主面在横向上延伸的字线，以激活在其中设置的晶体管。 另外的掺杂剂被引入位于字线之间的位线沟槽的沟槽壁中，以便在其上增加对应的晶体管导通电压以抑制漏电流。

    APPARATUS, METHOD AND SYSTEM FOR COMPARING SAMPLE DATA WITH COMPARISON DATA
    9.
    发明申请
    APPARATUS, METHOD AND SYSTEM FOR COMPARING SAMPLE DATA WITH COMPARISON DATA 审中-公开
    用于比较采样数据与比较数据的装置，方法和系统

    公开(公告)号：US20090006785A1

    公开(公告)日：2009-01-01

    申请号：US11769874

    申请日：2007-06-28

    申请人： Christoph Bilger ,  Rex Kho ,  Achim Schramm ,  Martin Maier ,  Yann Zinzius ,  Armin Kohlhase

    发明人： Christoph Bilger ,  Rex Kho ,  Achim Schramm ,  Martin Maier ,  Yann Zinzius ,  Armin Kohlhase

    IPC分类号： G06F12/00

    CPC分类号： G06F11/08 ,  G11C15/00

    摘要： An apparatus, method and system for comparing sample data with comparison date is disclosed. One embodiment provides a plurality of storage locations, an interface coupled to a plurality of storage locations for an exchange of data between the plurality of storage locations and external circuitry coupled to the interface, and a data comparator for comparing comparison data stored in the plurality of storage locations and sample data.

    摘要翻译： 公开了用于比较样本数据与比较日期的装置，方法和系统。 一个实施例提供多个存储位置，耦合到多个存储位置的接口，用于在多个存储位置之间交换数据和耦合到该接口的外部电路;以及数据比较器，用于比较存储在多个存储位置中的比较数据 存储位置和样本数据。

    Non-volatile memory cell and fabrication method
    10.
    再颁专利
    Non-volatile memory cell and fabrication method 有权
    非易失性存储单元及其制造方法

    公开(公告)号：USRE40532E1

    公开(公告)日：2008-10-07

    申请号：US11034444

    申请日：2005-01-11

    申请人： Josef Willer ,  Franz Hofmann ,  Armin Kohlhase ,  Christoph Ludwig

    发明人： Josef Willer ,  Franz Hofmann ,  Armin Kohlhase ,  Christoph Ludwig

    IPC分类号： H01L21/336 ,  H01L29/94

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： Memory cell transistors with back-channel isolation are produced without using an SOI substrate. With the word line stack acting as a mask, the semiconductor material is etched on both sides of the world line, first anisotropically and then isotropically to widen the etch hole and form an undercut beneath the gate electrode and at a distance from the ONO storage layer forming the gate dielectric. The undercut is filled, whereby a buried oxide layer of at least 20 nm maximum thickness is formed underneath the channel region. The latter is p-doped at a density of at least 1017 cm−3.

    摘要翻译： 在不使用SOI衬底的情况下制造具有背沟道隔离的存储单元晶体管。 利用字线叠层作为掩模，半导体材料在世界线的两侧蚀刻，首先各向异性地，然后各向同性地加宽蚀刻孔，并在栅电极下方并在与ONO存储层一定距离处形成底切 形成栅极电介质。 填充底切，由此在通道区域的下方形成最大厚度为至少20nm的掩埋氧化物层。 后者以至少10 17 cm -3的密度进行p掺杂。