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    FLAT PANEL DISPLAY AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    FLAT PANEL DISPLAY AND MANUFACTURING METHOD THEREOF 有权
    平板显示及其制造方法

    公开(公告)号：US20100123947A1

    公开(公告)日：2010-05-20

    申请号：US12534364

    申请日：2009-08-03

    申请人： DON-CHAN CHO ,  Jae-Byung Park ,  Jong-Hyuk Kang ,  Sung-Jin Hong ,  Yu-Kwan Kim ,  Seul Lee

    发明人： DON-CHAN CHO ,  Jae-Byung Park ,  Jong-Hyuk Kang ,  Sung-Jin Hong ,  Yu-Kwan Kim ,  Seul Lee

    IPC分类号： G02B26/00 ,  H01L21/77

    CPC分类号： G02B26/02 ,  H01L27/12

    摘要： A flat panel display includes a first substrate, a thin film transistor formed on the first substrate, a second substrate facing the first substrate, and a light controller formed on the second substrate, wherein the light controller is electrically connected to the thin film transistor, wherein the light controller includes an opening plate having a plurality of first openings and a light blocker moving horizontally with respect to the opening plate to selectively pass light through the first openings.

    摘要翻译： 平板显示器包括第一基板，形成在第一基板上的薄膜晶体管，面向第一基板的第二基板和形成在第二基板上的光控制器，其中光控制器电连接到薄膜晶体管， 其中所述光控制器包括具有多个第一开口的开口板和相对于所述开口板水平移动的光阻挡件，以选择性地将光通过所述第一开口。

    Flat panel display and manufacturing method thereof
    2.
    发明授权
    Flat panel display and manufacturing method thereof 有权
    平板显示及其制造方法

    公开(公告)号：US07973993B2

    公开(公告)日：2011-07-05

    申请号：US12534364

    申请日：2009-08-03

    申请人： Don-Chan Cho ,  Jae-Byung Park ,  Jong-Hyuk Kang ,  Sung-Jin Hong ,  Yu-Kwan Kim ,  Seul Lee

    发明人： Don-Chan Cho ,  Jae-Byung Park ,  Jong-Hyuk Kang ,  Sung-Jin Hong ,  Yu-Kwan Kim ,  Seul Lee

    IPC分类号： G02B26/02 ,  G02B26/00

    CPC分类号： G02B26/02 ,  H01L27/12

    摘要： A flat panel display includes a first substrate, a thin film transistor formed on the first substrate, a second substrate facing the first substrate, and a light controller formed on the second substrate, wherein the light controller is electrically connected to the thin film transistor, wherein the light controller includes an opening plate having a plurality of first openings and a light blocker moving horizontally with respect to the opening plate to selectively pass light through the first openings.

    摘要翻译： 平板显示器包括第一基板，形成在第一基板上的薄膜晶体管，面向第一基板的第二基板和形成在第二基板上的光控制器，其中光控制器电连接到薄膜晶体管， 其中所述光控制器包括具有多个第一开口的开口板和相对于所述开口板水平移动的光阻挡件，以选择性地将光通过所述第一开口。

    Semiconductor devices and methods of manufacturing the same
    5.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权
    半导体器件及其制造方法

    公开(公告)号：US09054226B2

    公开(公告)日：2015-06-09

    申请号：US13546415

    申请日：2012-07-11

    申请人： Sung-Ho Lee ,  Jin Choi ,  Yong-Ho Yoo ,  Jong-Hyuk Kang ,  Hyun-Joo Cha ,  Hee-Dong Park ,  Tae-Jung Park

    发明人： Sung-Ho Lee ,  Jin Choi ,  Yong-Ho Yoo ,  Jong-Hyuk Kang ,  Hyun-Joo Cha ,  Hee-Dong Park ,  Tae-Jung Park

    IPC分类号： H01L27/108 ,  H01L49/02

    CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/60

    摘要： A semiconductor device includes a plurality of lower electrodes on a substrate, with each of the lower electrodes extending in a height direction from the substrate and including sidewalls, the lower electrodes being spaced apart from each other in a first direction and in a second direction, a plurality of first supporting layer patterns contacting the sidewalls of the lower electrodes, the first supporting layer patterns extending in the first direction between ones of the lower electrodes adjacent in the second direction, a plurality of second supporting layer patterns contacting the sidewalls of the lower electrodes, the second supporting layer pattern extending in the second direction between ones of the lower electrodes adjacent in the first direction, the plurality of second supporting layer patterns being spaced apart from the plurality of first supporting layer patterns in the height direction.

    摘要翻译： 半导体器件包括在基片上的多个下电极，其中每个下电极从衬底沿高度方向延伸并且包括侧壁，下电极在第一方向和第二方向彼此间隔开， 与下电极的侧壁接触的多个第一支撑层图案，第一支撑层图案沿着第一方向在第二方向上相邻的下电极之间延伸;多个第二支撑层图案，其与下部电极的侧壁接触; 电极，所述第二支撑层图案沿着所述第二方向在与所述第一方向相邻的所述下电极中的所述第二方向延伸，所述多个第二支撑层图案在所述高度方向上与所述多个第一支撑层图案间隔开。

    Semiconductor devices and methods of forming semiconductor devices
    6.
    发明授权
    Semiconductor devices and methods of forming semiconductor devices 有权
    半导体器件和形成半导体器件的方法

    公开(公告)号：US08816417B2

    公开(公告)日：2014-08-26

    申请号：US12659111

    申请日：2010-02-25

    申请人： Sanghun Jeon ,  Jong-Hyuk Kang ,  Heungkyu Park ,  Jongwook Lee

    发明人： Sanghun Jeon ,  Jong-Hyuk Kang ,  Heungkyu Park ,  Jongwook Lee

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L29/7841 ,  H01L27/108 ,  H01L27/10802

    摘要： A semiconductor device includes a back bias dielectric including a negative fixed charge, a gate electrode overlapping the back bias dielectric, a semiconductor layer disposed between the gate electrode and the back bias dielectric, and a gate dielectric disposed between the semiconductor layer and the gate electrode, wherein the negative fixed charge accumulates holes at a surface of the semiconductor layer facing the back bias dielectric.

    摘要翻译： 半导体器件包括负偏电介质，其包括负的固定电荷，与所述背偏电介质重叠的栅电极，设置在所述栅电极和所述背偏置电介质之间的半导体层，以及设置在所述半导体层和所述栅电极之间的栅极电介质 其中负固定电荷在面向背偏电介质的半导体层的表面处累积空穴。

    Vertical-type semiconductor device
    8.
    发明授权
    Vertical-type semiconductor device 有权
    垂直型半导体器件

    公开(公告)号：US07960780B2

    公开(公告)日：2011-06-14

    申请号：US12478081

    申请日：2009-06-04

    申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： H01L29/772 ,  H01L21/8242

    CPC分类号： H01L29/7827 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7841

    摘要： In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.

    摘要翻译： 在垂直型半导体器件中，其制造方法及其操作方法，垂直型半导体器件包括：具有设置在基板上的柱状的单晶半导体图案， 单晶半导体图案，并且具有比单晶半导体图案的上表面低的上表面，形成在栅极的上表面上的掩模图案，所述掩模图案具有与单个半导体图案的上表面共面的上表面 晶体半导体图案，在单晶半导体图案下的衬底中的第一杂质区域和在单晶半导体图案的上表面下方的第二杂质区域。 形成在单晶半导体图案中的垂直型立柱晶体可以提供优异的电性能。 在第二杂质区域中的单晶半导体图案的上表面上没有设置掩模图案，从而减少处理的失败。

    VERTICAL TYPE SEMICONDUCTOR DEVICE
    9.
    发明申请
    VERTICAL TYPE SEMICONDUCTOR DEVICE 失效
    垂直型半导体器件

    公开(公告)号：US20100123182A1

    公开(公告)日：2010-05-20

    申请号：US12620923

    申请日：2009-11-18

    申请人： Yong-Hoon SON ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon SON ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： H01L29/792

    CPC分类号： H01L21/28282 ,  H01L27/11578 ,  H01L29/66833 ,  H01L29/7923

    摘要： A vertical pillar semiconductor device includes a substrate, a single crystalline semiconductor pattern, a gate insulation layer structure and a gate electrode. The substrate may include a first impurity region. The single crystalline semiconductor pattern may be on the first impurity region. The single crystalline semiconductor pattern has a pillar shape substantially perpendicular to the substrate. A second impurity region may be formed in an upper portion of the single crystalline semiconductor pattern. The gate insulation layer structure may include a charge storage pattern, the gate insulation layer structure on a sidewall of the single crystalline semiconductor pattern. The gate electrode may be formed on the gate insulation layer structure and opposite the sidewall of the single crystalline semiconductor pattern. The gate electrode has an upper face substantially lower than that of the single crystalline semiconductor pattern.

    摘要翻译： 垂直柱半导体器件包括衬底，单晶半导体图案，栅极绝缘层结构和栅电极。 衬底可以包括第一杂质区域。 单晶半导体图案可以在第一杂质区上。 单晶半导体图案具有基本上垂直于基板的柱形。 可以在单晶半导体图案的上部形成第二杂质区。 栅极绝缘层结构可以包括电荷存储图案，单晶半导体图案的侧壁上的栅极绝缘层结构。 栅电极可以形成在栅极绝缘层结构上并且与单晶半导体图案的侧壁相对。 栅电极具有比单晶半导体图案基本上低的上表面。

    Semiconductor memory device and method of manufacturing the same
    10.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US08294209B2

    公开(公告)日：2012-10-23

    申请号：US12659076

    申请日：2010-02-24

    申请人： Sanghun Jeon ,  Jongwook Lee ,  Jong-Hyuk Kang ,  Heungkyu Park

    发明人： Sanghun Jeon ,  Jongwook Lee ,  Jong-Hyuk Kang ,  Heungkyu Park

    IPC分类号： H01L29/94

    CPC分类号： H01L27/105 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844

    摘要： A semiconductor memory device includes a plurality of active pillars protruding from a semiconductor substrate, a first gate electrode disposed on at least one sidewall of the active pillar, a first gate insulating layer being disposed between the active pillar and the first gate electrode, a second gate electrode disposed on at least one sidewall of the active pillar over the first gate electrode, a second gate insulating layer being disposed between the active pillar and the second gate electrode, first and second body regions in the active pillar adjacent to respective first and second respective electrodes, and first through third source/drain regions in the active pillar arranged alternately with the first and second body regions.

    摘要翻译： 半导体存储器件包括从半导体衬底突出的多个有源柱，设置在有源柱的至少一个侧壁上的第一栅电极，设置在有源柱和第一栅电极之间的第一栅极绝缘层， 栅电极设置在所述有源柱的至少一个侧壁上，位于所述第一栅极上，第二栅极绝缘层，设置在所述有源柱和所述第二栅极之间，所述有源支柱中的第一和第二主体区域与相应的第一和第二栅极相邻; 各个电极以及有源柱中的第一至第三源极/漏极区域与第一和第二主体区域交替布置。