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公开(公告)号：US06990035B2
公开(公告)日：2006-01-24
申请号：US10727888
申请日：2003-12-03
IPC分类号： G11C7/00
CPC分类号： G11C11/417
摘要： A method of operating a memory circuit to reduce standby current is disclosed. The method includes applying a first voltage (Vdd) to a power terminal (224) of a memory cell having a first (612) and a second (614) data terminal. A data bit is stored in a memory cell (600,602,604,606). A second voltage (VDA) different from the first voltage is applied to the power terminal. A third voltage (Ground) is applied to the first and second data terminals. The first voltage is applied to the power terminal.
摘要翻译： 公开了一种操作存储电路以减少待机电流的方法。 该方法包括将第一电压（Vdd）应用于具有第一（612）和第二（614）数据端的存储单元的电源端子（224）。 数据位存储在存储单元（600,602,604,606）中。 与第一电压不同的第二电压（VDA）被施加到电源端子。 第三电压（Ground）被施加到第一和第二数据端子。 第一个电压被施加到电源端子。
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2.发明授权Method of forming high density DRAM having increased capacitance area due to trench etched into storage capacitor region 失效形成由于沟槽蚀刻到存储电容器区域中而增加的电容面积的高密度DRAM的方法
公开(公告)号：US5374580A
公开(公告)日：1994-12-20
申请号：US129011
申请日：1993-09-30
IPC分类号： H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10829 , Y10S438/981
摘要： A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar in structure to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.
摘要翻译： 动态单晶体管读/写存储单元采用沟槽电容器来增加存储电荷的大小。 在与N +位线结构相似的扩散的N +电容器区域，将沟槽蚀刻到硅表面中，然后在位线上和电容器区域上而不是在沟槽中生长厚的氧化物。 电容器的上板是延伸到沟槽中的多晶硅层，并且还在硅棒的表面上形成场板隔离。 难熔金属字线在多晶硅场板的一个孔处形成存取晶体管的栅极。
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公开(公告)号：US5170234A
公开(公告)日：1992-12-08
申请号：US758318
申请日：1991-08-27
IPC分类号： H01L27/108
CPC分类号： H01L27/10829 , Y10S438/981
摘要： A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar in structure to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A word line forms the gate of the access transistor at a hole in the polysilicon field plate.
摘要翻译： 动态单晶体管读/写存储单元采用沟槽电容器来增加存储电荷的大小。 在与N +位线结构相似的扩散的N +电容器区域，将沟槽蚀刻到硅表面中，然后在位线上和电容器区域上而不是在沟槽中生长厚的氧化物。 电容器的上板是延伸到沟槽中的多晶硅层，并且还在硅棒的表面上形成场板隔离。 字线在多晶硅场板的孔处形成存取晶体管的栅极。
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公开(公告)号：US5156992A
公开(公告)日：1992-10-20
申请号：US720542
申请日：1991-06-25
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10841
摘要： A memory cell comprises a semiconductor pillar and an insulator on a sidewall of the pillar. A conductive capacitor of the memory cell comprises a first electrode adjacent the insulator. A transistor of the memory cell is formed in the pillar and comprises a first source/drain region, a gate, and a second source/drain region coupled to the first electrode.
摘要翻译： 存储单元包括在柱的侧壁上的半导体柱和绝缘体。 存储单元的导电电容器包括邻近绝缘体的第一电极。 存储单元的晶体管形成在柱中，并且包括耦合到第一电极的第一源极/漏极区域，栅极和第二源极/漏极区域。
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公开(公告)号：US5300450A
公开(公告)日：1994-04-05
申请号：US951639
申请日：1992-09-25
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A DRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD. The word line is formed closely adjacent the pillars in its associated row,, separated therefrom by a gate dielectric film; the word line is separated from the adjacent row by a dielectric film which is thicker than the gate dielectric, so that the word line will cause conduction between the inversion region and the top diffusion for its associated row, but not for the adjacent row.
摘要翻译： 公开了DRAM存储单元结构及其形成方法。 每个存储单元形成在柱上，其中存储板是由围绕每个柱的所有侧面的场板产生的反转区域，并由存储电介质膜分离。 场板形成为栅格形状，并且设置在围绕柱阵列的沟槽的底部，以用作阵列中的所有存储电容器的固定板。 每个支柱的顶部是位线连接到的扩散部分。 放置在场板上方的沟槽中并沿一个方向延伸的是字线。 每个字线由通过选择性CVD沉积钨的多晶硅细丝形成。 字线与其相关联的行中的柱紧邻地形成，通过栅极电介质膜与其分离; 字线通过比栅极电介质厚的电介质膜与相邻行分离，使得字线将引起反转区域与其相关行的顶部扩散之间的导通，但不会导致相邻行的导通。
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公开(公告)号：US4958212A
公开(公告)日：1990-09-18
申请号：US292285
申请日：1988-12-30
申请人： Clarence W. Teng , William F. Richardson , Robert R. Doering , Ashwin H. Shah , Bing W. Shen , Mark Bordelon
发明人： Clarence W. Teng , William F. Richardson , Robert R. Doering , Ashwin H. Shah , Bing W. Shen , Mark Bordelon
IPC分类号： H01L27/108
CPC分类号： H01L27/10841
摘要： An improved memory cell layout (54) is formed including a trench cell (60) formed in a semiconductor substrate (58). The memory cell layout (54) includes a bitline (56) and a wordline (62) for storing and accessing charge. The charge is stored on a capacitor formed from a conductor (68), an insulating region (70) and a semiconductor substrate (58). Bitline (56) is primarily tangential to a trench cell (60), or may surround the periphery thereof. A wordline (62) overlies trench cell (60) and extends therein, and further may be formed of a width narrower than trench cell (60).
摘要翻译： 形成改进的存储单元布局（54），包括形成在半导体衬底（58）中的沟槽单元（60）。 存储单元布局（54）包括用于存储和访问电荷的位线（56）和字线（62）。 电荷存储在由导体（68），绝缘区（70）和半导体衬底（58）形成的电容器上。 位线（56）主要与沟槽单元（60）相切，或者可以围绕其周边。 字线（62）覆盖在沟槽单元（60）上并在其中延伸，并且还可以由窄于沟槽单元（60）的宽度形成。
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公开(公告)号：US4882649A
公开(公告)日：1989-11-21
申请号：US174751
申请日：1988-03-29
申请人： Ih-Chin Chen , Bing W. Shen , Robert R. Doering
发明人： Ih-Chin Chen , Bing W. Shen , Robert R. Doering
IPC分类号： H01G4/20 , H01L27/108 , H01L29/94
CPC分类号： H01G4/20 , H01L27/10829 , H01L29/945 , Y10T29/435
摘要： An integrated circuit capacitor is disclosed which has improved leakage and storage characteristics. The dielectric material for the capacitor consists of a first layer of silicon nitride adjacent the lower plate, such as a silicon substrate, upon which a layer of silicon dioxide is formed. A second layer of silicon nitride is formed over the silicon dioxide layer, above which the second plate is formed. The layer of silicon dioxide may be formed by the partial oxidation of the first silicon nitride layer. The capacitor may be a planar capacitor, may be formed in a trench, or may be formed between two layers above the surface of the substrate.
摘要翻译： 公开了一种具有改进的泄漏和存储特性的集成电路电容器。 用于电容器的电介质材料包括邻近下板的第一层氮化硅，例如硅衬底，在其上形成二氧化硅层。 在二氧化硅层上形成第二层氮化硅，在其上形成第二板。 二氧化硅层可以通过第一氮化硅层的部分氧化形成。 电容器可以是平面电容器，可以形成在沟槽中，或者可以形成在衬底表面之上的两层之间。
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8.发明授权Method of making MOS VLSI semiconductor device with metal gate and clad source/drain 失效制造具有金属栅极和包层源极/漏极的MOS VLSI半导体器件的方法
公开(公告)号：US4661374A
公开(公告)日：1987-04-28
申请号：US638440
申请日：1984-08-07
申请人： Robert R. Doering
发明人： Robert R. Doering
IPC分类号： H01L29/78 , H01L21/285 , H01L21/336 , H01L21/28
CPC分类号： H01L29/66575 , H01L21/28518 , Y10S438/902 , Y10T156/178
摘要： Metal-gate transistors with metal silicide cladding of the source/drain regions, as may be used in very high density dynamic RAM devices, are made by a process in which the metal gate is encapsulated in oxide and the cladding is self aligned with the encapsulated gate. A thin coating of a refractory metal is applied to the source/drain areas and heated to react with the exposed silicon. The unreacted metal is removed by an etchant that does not disturb the metal gate or the silicide.
摘要翻译： 可以用于非常高密度的动态RAM器件中的源/漏区金属硅化物包层的金属栅极晶体管通过其中金属栅极被封装在氧化物中并且包层与封装的自对准的过程 门。 将难熔金属的薄涂层施加到源极/漏极区域并加热以与暴露的硅反应。 通过不干扰金属栅极或硅化物的蚀刻剂除去未反应的金属。
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公开(公告)号：US5103276A
公开(公告)日：1992-04-07
申请号：US200823
申请日：1988-06-01
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A dRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD. The word line is formed closely adjacent the pillars in its associated row, separated therefrom by a gate dielectric film; the word line is separated from the adjacent row by a dielectric film which is thicker than the gate dielectric, so that the word line will cause conduction between the inversion region and the top diffusion for its associated row, but not for the adjacent row.
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公开(公告)号：US4958206A
公开(公告)日：1990-09-18
申请号：US212452
申请日：1988-06-28
IPC分类号： H01L27/108
CPC分类号： H01L27/10829
摘要： A trench (28) of a DRAM cell is formed in a (p-) epitaxial layer (10) and a silicon substrate (12), and a storage oxide (32) is grown on the sidewalls (30) of the trench (28). A highly doped polysilicon capacitor electrode (34) is formed in the trench (28). A portion (52) of the storage oxide (32) is removed from a selected side of the sidewalls (30), and a plug (68) is deposited therein and etched back so that the electrode (34) is connected to the epitaxial layer (10). A thermal cycle is used to diffuse dopant from the capacitor electrode (34) into and through the plug (68) and into the adjacent semiconductor layer (10) to make the plug (68) conductive and to form a source region (66) of a pass gate transistor of the cell.
摘要翻译： 在（p-）外延层（10）和硅衬底（12）中形成DRAM单元的沟槽（28），并且在沟槽（28）的侧壁（30）上生长存储氧化物（32） ）。 在沟槽（28）中形成高掺杂多晶硅电容器电极（34）。 存储氧化物（32）的一部分（52）从侧壁（30）的选定侧被去除，并且在其中沉积插塞（68）并被回蚀，使得电极（34）连接到外延层 （10）。 热循环用于将掺杂剂从电容器电极（34）扩散入并穿过插塞（68）并进入相邻的半导体层（10）以使插头（68）导电并形成源极区域（66） 电池的通栅晶体管。
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